Multi$-$cycle synchronous neuron datapath core

m x q unsigned integer multiplier with synchronous output: Synapses will be modeled by

combinational m x q unsigned integer multipliers with each xi input of size m bits and each weight of

size q bits. You will implement a register with update control $($in addition to clk control$)$ at the output

of the multiplier such that a computed output will only be available on the rising edge of the clk if

update signal is ON$.$ If update is OFF, the register will retain its previous value.

Code:

module MxQ$\_$Multi$($M$,$Q$,$P$)$;

input$[2$:$0]$M;

input$[1$:$0]$Q;

output$[4$:$0]$P:

output control;

wire$[2$:$0]$X$,$Y$,$S;

wire carryout;

assign Y $=\{1\text{'}$b$0,$M$[2]$&Q$[0],$M$[1]$&Q$[0]\}$;

assign X $=\{$M$[2]$&Q$[1],$M$[1]$&Q$[1],$M$[0]$&Q$[1]\}$;

nbit$\_$RCA M$1(1\text{'}$b$0,$Y$,$X$,$S$,$carryout$)$;

defparam M$1.$n $=3$;

assign P $=\{$carryout$,$S$,$M$[0]$&Q$[0]\}$;

endmodule

$4-$input n$-$bit adder: Generate an adder unit that can add four n$-$bit numbers as part of the neuron

function y$.$ You will need to figure out how many bits you need to allow for the output for any n$.$

Code:

module nbit$\_$RCA $($carryin$,$X$,$Y$,$S$,$carryout$)$;

parameter n$=4$;

input carryin;

input $[$n$-1$:$0]$X$,$Y;

output$[$n$-1$:$0]$S;

output carryout;

wire $[$n:$0]$C;

genvar i;

assign C$[0]=$ carryin;

assign carryout $=$ C$[$n$]$;

generate

for$($i$=0$; in$-1$; i$=$i$+1)$

begin: fulladder$\_$RCA

full$\_$adder M $($C$[$i$],$X$[$i$],$Y$[$i$],$S$[$i$],$C$[$i$+1])$;

end

endgenerate

endmodule

Unsigned division by $2$n: Generate a combinational divider function that divides an unsigned m$-$bit

input integer by a power of $2(2$n$)$ to generate a smaller unsigned integer. This is the second operation

in the neuron function y$.$ How many bits is the smaller unsigned integer at the output?

Code:

module div$\_$by$\_2$n #$($parameter m$=4,$ parameter n$=1)($M$,$Q$)$;

input $[$m$-1$:$0]$M;

output $[$m$-1-$n:$0]$Q;

assign Q $=$ M $>>$ n;

endmodule

Develop a Verilog HDL testbench to do corner$-$case verification of $10$ consecutive input xi patterns to

verify the basic functionality of datapath core e$.$g$.$ weight and Prediction counters counting in the

right direction. Achieving a firing event.