Question: Need this to do signed numbers it currently does unsigned. It is in system verilog. Also can't use 'signed' function. module Multiplier ( input Clock,

Need this to do signed numbers it currently does unsigned. It is in system verilog. Also can't use 'signed' function.
module Multiplier (
input Clock, Reset, //declare inputs
input [3:0]Multip1icand,
input [3:0]Multiplier,
output [7:0]Product,//declare outputs
output Halt);
reg [3:0]RegQ, RegM; //Q and M registers
reg [4:0]RegA; //A register
reg [1:0]count; //2-bit iteration counter
wire co,Start, Add, shift;
assign Product ={RegA[3:0],RegQ}; //product =A:Q
//2-bit counter for #iterations
always @(posedge Clock)
if (Start ==1)Count <=2'b00; //clear in start state
else if (shift ==1)Count }<=\mathrm{Count +1; //increment in shift state
assign CO =Count [1]& Count [0]; //detect count =3
//Mult1plicand register (load only)
always @(posedge clock)
if (Start ==1)RegM <=Multiplicand; //load in start state
//Multiplier register (load,shift)
always @(posedge Clock)
if (Start ==1)RegQ <=Multiplier; //load in start state
else if (shift ==1)RegQ <={RegA[0],RegQ[3:1]}; //shift in shift state
//Accumulator register (clear,load, shift)
always @(posedge Clock)
if (Start ==1)RegA <=5'b00000; //clear in start state
else if (Add ==1)RegA <=RegA +RegM; //7oad in Add state
//Instantiate controller module
Multcontrol Ctr1(Clock,Reset, RegQ[0],C0,Start, Add, Shift, Halt);
endmodule
module MultContro1(
input Clock, Reset, QO,CO,//declare inputs
output Start, Add, shift, Ha7t); //declare outputs
reg [4:0]state; //five states (one hot -one flip-flop per state)
//one-hot state assignments for five states
parameter starts=5'b00001,TestS=5'b00010,Adds=5'b00100,shifts=5'b01000,
reg [1:0]Counter; //2-bit counter for # of algorithm iterations
//state transitions on positive edge of Clock or Resets
always @(posedge Clock, posedge Reset)
if (Reset==1)state <=Starts; //enter starts state on Reset
else
case (state)
Starts: state <=Tests; //starts to Tests
TestS: if (QO)state <=AddS; //TestS to AddS if Q0=1
else state <=shifts; //Tests to shifts if Q0=0
Adds: state <=shifts; //Adds to shifts
Shifts: if (CO)state <=Halts; //shifts to Halts if C0=1
else state <=Tests; //shifts to Tests if c0=0
Halts: state <=Halts; //stay in Halts
endcase
Moore model -activate one output per state
assign Start =state[0]; //Start=1in state Starts, else 0
assign Add =state[2]; //Add=1in state Adds, else 0
assign shift =state[3]; //shift=1in state shifts, else 0
assign Halt =state[4]; //Halt=1in state Halts, else 0
endmodule

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