Part $1$:

Single$-$Cycle Implementation:

$-$ Design the datapath for the below given instruction set with the control unit.

i$.$ R$-$type instructions

$-$ ALU functions $($ADD$,$ SUB, OR$,$ AND, SLT$,$ and at least $1$ additional function$)$

ii$.$ I$-$type instructions

$-$ LW$,$ SW$,$ ADDI, SUBI, ORI, ANDI, BEQ, BNE, and at least $1$ additional function

iii. J and JAL

$-$ Tabulate the Control signals and the ALU Control for the given Instruction set.

$-$ Write the SystemVerilog code for the whole design and the Testbench code to simulate the implemented design.

$-$ Run a sample code for simulation to show the implemented Single$-$Cycle Processor