Please show work:

In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: Also, assume that instructions executed by the processor are broken down as follows: [5]

What is the clock cycle time in a pipelined and non-pipelined process? [10]

What is the total latency of an LW instruction in a pipelined and non-pipelined processor