Question: Problem 2: This problem refers to the figure shown in Problem-1 without any modifications. The logic blocks used to implement the datapath have the following

Problem 2: This problem refers to the figure shown in Problem-1

Problem 2: This problem refers to the figure shown in Problem-1 without any modifications. The logic blocks used to implement the datapath have the following latencies: I-Mem Add Mux ALU Regs D-Mem Sign-Shif ALU 200ps 70ps 20ps 90ps 90ps 250ps 15ps 10ps30ps a) To avoid lengthening the critical path of the datapath, how much time can the ExtendLeft-2Ctrl control unit take to generate the MemWrite signal? b) Which control signal is the most critical to generate quickly and how much time can the control unit take if it wants to avoid being on the critical path

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