Question: Question : Use the following code fragment: Loop: ld x 1 , 0 ( x 2 ) ; load x 1 from address 0 +

Question :

Use the following code fragment:

Loop: ld x

1, 0 (

2)

; load x

1

from address

0 +

2

addi x

1,

1, 1

; x

1 =

1 + 1

sd x

1, 0, (

2)

; store x

1

at address

0 +

2

addi x

2,

2, 4

; x

2 =

2 + 4

sub x

4,

3,

2

; x

4 =

3 -

2

bnez x

4,

Loop; branch to Loop if x

4! = 0

Assume that the initial value of

x 3

x 2 + 396 .

Show the timing of this instruction sequence for the

5 -

stage RISC pipeline without any forwarding or

bypassing hardware but assuming that a register read and a write in the same clock cycle "forwards" through

the register file, as between the add and or shown in Figure C

. 5

of Appendix C

.

Use a pipeline timing chart like

that in Figure C

. 8

of Appendix C

.

Assume that the branch is handled by flushing the pipeline. If all memory references take

1

cycle, how many

cycles does this loop take to execute?

Book to refer: Morgan Kaufman Introduction to Computer Architecture Principles

Question : Use the following code fragment: Loop: ld x1,0(x2); load

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