Referring to the parallel$-$access shift register in Figure $7\mathrm{.}19$ and Slide $5$ Module $69,$ fill in the following table:

Serial Input $!$Shift$/$Load Parallel input Q$3$ Q$2$ Q$1$ Q$0$

t$01100001010$

t$1100001$

t$2000010$

t$3100011$

t$4000100$

t$5100101$

t$6000110$

t$7000111$

If the first bit out is the least$-$significant$-$bit and the last bit out is the most$-$significant$-$bit, the output of Q$0$ for t$1-$t$7=$