RISC-V ASSEMBLY LANGUAGE

Assume that the single-instruction/cycle datapath shown below Add 4 Add Sum Shift left 1 Branch MemRead MemtoRe Instruction [6-0] Control ALU MemWrite ALUSrc RegWrite Instruction [19-15]Read Read address register 1 Read PC Instruction [24-20] data 1 Read register 2 Write Read register data 2 Write data Registers Instruction ALU ALU result [31-0]Instruction [11.7] Read Address data Instruction memory Write Data data memo Instruction (31032Imm 64 ALU control Gen Instruction [30,14-12) Assume the latencies of the Datapath components are 40 ps for Program Counter, 260 ps for Instruction Memory, 160 ps for the register file, 20 ps for Multiplexors, 200 ps for the ALU, 140 ps for Adder, logic gate2 ps, immediate generator 40 ps, shift left 10 ps, Data Memory 280 ps, Control block 60 ps a) How long must the clock period be for complete execution of an add instruction? b) What is the clock cycle time to accommodate a beq instruction (what is the critical path for that instruction)? c) If the same architecture also had to execute ld instruction, will the clock cycle be the same? Why yeso? d) What is the clock frequency which accommodates all three instructions? e) Assume that the app being executed has 50% R-type instructions, 30 % ld instructions and the remainders are all branch instructions. If we had a Datapath that allows modification of clock cycle