Question: Sketch a 4 - input Static CMOS NAND gate with transistor widths chosen to achieve equal rise and fall resistance as a unit inverter. (

Sketch a 4-input Static CMOS NAND gate with transistor widths chosen to achieve equal rise and fall resistance as a unit inverter. (Assume =3).
Derive the delay versus fanout (d-h) plot for the same NAND gate.
Sketch a 4 - input Static CMOS NAND gate with

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