Sketch the equivalent circuit described by this VHDL entity. entity X is port (X,Y,Z in std...

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Sketch the equivalent circuit described by this VHDL entity. entity X is port (X,Y,Z in std logic; out std logic); q,r end X; architecture behaviour of X is signal int : std_logic; begin int <= X and Y; Q <= int OR Z; R <= int; end behaviour; Sketch the equivalent circuit described by this VHDL entity. entity X is port (X,Y,Z in std logic; out std logic); q,r end X; architecture behaviour of X is signal int : std_logic; begin int <= X and Y; Q <= int OR Z; R <= int; end behaviour;