Task B: Implement logic block in Vivado

$2.$ In your Vivado project, create a new design source file for the Logic Block. Name the circuit LogicBIk. As expected, your module should have one output $($y$)$ and four inputs $(a,b,s0,s1).$

$3.$ Using your Logic Block planning schematic and the functionality described above, follow the guidelines below to implement the circuit in Verilog.

a$.$ add any wire signals necessary to define internal signals $($ones that are not module ports$)$ needed to connect circuits together

b$.$ create an assign statement for each of the four logic functions

c$.$ use an instantiation statement to add the MUX$\_41$ you designed in Exercise $2$

d$.$ ask your lab mates or your TA for help if you are having difficulty creating the circuitry

$4.$ Once finished, ask your TA to perform a check$-$in and verify that your module code looks correct.

$5.$ Record the final LogicBlk module Verilog description in your Worksheet.

Task C: Test logic block

Before creating a testbench, let's think about what we need to test.

$6.$ Locate the "LogicBlk test table" in your Worksheet and try to predict the logic block functionality, based on theory. First, notice that each row is a different combination of select signals, $s1,s0.$ Then fill in the logic function assigned to each row in the "logic function" column. Finally, fill in the "expected y$"$ column for each row.

Notice here we have $4$ inputs and would need $16$ test values to test call combinations. If you were building a commercial product, that is certainly something you would do$.$ However, to reduce time in this lab, we are just going to test each of the four logic functions for a fixed value of data inputs a and $b.$ Here we have chosen to set $a=1$ and $b=0,$ and we'll move forward under the $($somewhat dubious$)$ assumption that, if it works for one set of data inputs it should work for others.

$7.$ Next, create a testbench for LogicBIk called LogicBlk$\_$tb with output $($wire$)Y$ and