The pipelined MIPS implementation in Question 4 can be modified to resolve data hazards through Forwarding. Draw a possible internal circuit diagram of the Forwarding Unit shown in the datapath below. IDEX WB EX/MEM Control M MEMWB IF/ID WBE WB EX M Instruction Registers ALU PC Instruction memory Data memory IF/ID. Registers IF/ID.Register IF/ID. Registert IF/ID. RegisterRd Rs RI Rt Ral EX/MEM. RegisterRd Forwarding unit MEMWB. RegisterRd The pipelined MIPS implementation in Question 4 can be modified to resolve data hazards through Forwarding. Draw a possible internal circuit diagram of the Forwarding Unit shown in the datapath below. IDEX WB EX/MEM Control M MEMWB IF/ID WBE WB EX M Instruction Registers ALU PC Instruction memory Data memory IF/ID. Registers IF/ID.Register IF/ID. Registert IF/ID. RegisterRd Rs RI Rt Ral EX/MEM. RegisterRd Forwarding unit MEMWB. RegisterRd