Question: The waveforms in figure (1) are the input test vectors used for the simulation of the VHDL code listed below. Predict the output vectors y_out

The waveforms in figure (1) are the input test vectors used

The waveforms in figure (1) are the input test vectors used for the simulation of the VHDL code listed below. Predict the output vectors y_out for each interval. Provide the answer in hexadecimal numbers, library ieee; use ieee.std_logic_1164.all; entity HW_2 is port( x_in in std_logic_vector (7 downto 0); y_out out std_logic_vector (7 downto 0)); end entity; architecture question of HW_2 is begin L1: for i in o to 7 generate y_out(7-1)

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