The waveforms in figure (3) are the input test vectors used for the simulation of the VHDL code listed below. Predict the output vectors y" and "ready" for each interval. library ieee; use ieee.std_logic_1164.all; entity HW_2 is port( cs_n sin std_logic; -- active low xin :in std_logic_vector (3 downto 0); :out std_logic_vector (1 downto 0); ready :out std_logic); end entity; architecture question of Hw_2 is signal m:std_logic_vector (2 downto 0); begin with xin select m