The waveforms in figure (5) are the input test vectors used for the simulation of the VHDL code listed below. Predict the output vectors y for each interval. user hele star logic_1164. all; entity HW_2 is port(a, b, c std_logic; :out std_logic); end entity; architecture question of HW_2 is begin process(a, b, c) begin if c='0' then y