The waveforms in figure (4) are the input test vectors used for the simulation of the VHDL code listed below. Predict the output vectors y_out" for each interval. Provide the answer in hexadecimal numbers. userar med stologic_1164. all; entity HW_2 is port(load, clk, reset_n :std_logic; x_in in std_logic_vector (downto 0);. y-out out std_logic_vector (7 downto 0)); end entity; architecture question of ww_2 is begin process variable q : std_logic_vector (7 downto 0); begin wait until (rising_edge(cik)); if reset_n = '' then 9:= "00000000"; elsif load = '1' then 9.:= x_in; end if; y_out