The waveforms in figure (2) are the input test vectors used for the simulation of the VHDL code listed below. Predict the output vectors y" for each interval. library ieee; use ieee.std_logic_1164.all; entity HW_2 is port(a, b, c, d sin std_logic; sout std_logic); end entity; architecture question of ww_2 is signal mustd_logic; begin y