Verilog module:

module test$($output $[1$:$0]$ Q$,$ input x$,$ input clock, input reset$)$;

reg $[1$:$0]$ state;

parameter $SO=2^{\text{'}}b00,S1=2^{\text{'}}b01,S2=2\text{'}b10,S3=2^{\text{'}}b11$;

always @ $($posedge clock, negedge reset$)$

if$($treset$)$ state $=50$;

else case$($state$)$

SO: $if(x)$ state $,$; else state $$

S$1$: if $(x)$ state $$ Select answer $,$; else state $$

S$2$: if $(x)$ state $$ Select answer $,$ : else state $$ Select answer ;

S$3$: if $(x)$ state $$ Select answer ; ise state $$

endcase

assign $Q=$ state;

endmodule