Verilog module:

module test$($output $[1$:$0]$ Q$,$ input x$,$ input clock, input reset$)$;

reg $[1$:$0]$ state;

parameter S$0=2\text{'}$b$00,$ S$1=2\text{'}$b$01,$ S$2=2\text{'}$b$10,$ S$3=2\text{'}$b$11$;

always @ $($posedge clock, negedge reset$)$

if$(!$reset$)$ state$<=$S$0$;

else case$($state$)$

S$0$: if$($x$)$ state$<=$ ; else state$<=$ ;

S$1$: if$($x$)$ state$<=$ ; else state$<=$ ;

S$2$: if$($x$)$ state$<=$ ; else state$<=$ ;

S$3$: if$($x$)$ state$<=$ ; else state$<=$ ;

endcase

assign Q$=$state;

endmodule

Testbench:

module t$\_$test;

reg x; reg clock; reg reset;

wire $[1$:$0]$ Q;

test uut $($Q$,$x$,$clock,reset$)$;

initial begin

x$=1$; clock$=0$; reset$=0$;

#$1$; reset $=1$;

# ; reset$=0$; x$=0$;

#$1$; reset$=1$;

end

always # clock$=$~clock;

initial # $finish;

endmodule