Verilog module:

module test$($output $[1$:$0]$ Q$,$ input x$,$ input clock, input reset$)$;

reg $[1$:$0]$ state;

parameter $S0=2^{\text{'}}b00,S1=2b01,S2=2b10,S3=2^{\text{'}}b11$;

always @ $($posedge clock, negedge reset$)$

if$(!$reset$)$ stateS$0$;

else case$($state$)$

endcase

assign Q$=$state;

endmodule

Testbench:

module t$\_$test;

reg x; reg clock; reg reset;

wire $[1$:$0]$ Q;

test uut $($Q$,$x$,$clock,reset$)$;

initial begin

$x=0$; clock$=0$; reset$=0$;

#$2$; reset $=1$;

#

; reset$=0$; $x=1$;

#$2$; reset$=1$;

end

always #

clock$=$ clock;

initial #

$finish;

endmodule