What are the errors in the following VHDL code:

entity 4tol_mux port ( signal a, b, c, d: std_logic_vectors(3 downto 0);

select: in std_logic_vector(l downto 0);

x: out bit_vector(3 downto 0);

end;

architecture of 4tol_mux

begin

pl: process begin

if select = '00' then

x <= a;

elsif select = '10'

x <= b;

elsif select = '11'

x <= c; else

x <= d

end if;

end process;

end 4tol_mux;