What is the function implemented by the following Verilog modules:

module FUNC1 (I0, I1, S, out);

input I0, I1;

input S;

output out;

out = S? I1: I0;

endmodule

module FUNC2 (out,ctl,clk,reset);

output [7:0] out;

input ctl, clk, reset;

reg [7:0] out;

always @(posedge clk)

if (reset) begin

out <= 8b0 ;

end

else if (ctl) begin

out <= out + 1;

end

else begin

out <= out - 1;

end

endmodule