When processor designers consider a possible improvement to the processor data path, the decision usually depends on the cost/performance trade-off. In the following three problems, assume that we are starting with a data path from Figure 1, where I-Mem, Add, Mux, ALU, Regs, D-Mem, and Control blocks have latencies of 400 ps, 100 ps, 30 ps, 120 ps, 200 ps, 350 ps, and ps, respectively, and costs of 1000, 30, 10, 100, 200, 2000, and 500, respec tively Consider the improvement of the I-Mem. This improvement will reduce 200 ps to the latency of the I-Mem and will add a cost of 300 to the I-Mem 100 Bsanh Add ALU operat Data MeniWrte Registers ALU Address PC-Address Instruction Instruction memory Register # Data memory Register # RegWrite . x Data MemRead Control a) What is the clock cycle time with and without this improvement? b) What is the speedup achieved by adding this improvement?(3 points c)What is the cost with and without this improvement?(4 points) d)Compare the cost/performance ratio with and without this improve ment