When the processor designers consider adding a new instruction to the processor datapath, the decision usually depends on the cost$/$performance trade$-$offs. In the following three sections, assume that we are starting with the datapath given to you:

Also, the logic blocks used to implement this datapath have the following latencies: Inst. Mem. Adder Mux ALU Reg. file $($R$/$W$)$ Data Mem. Control Block Imm. Gen. $400$ps $80$ps $10$ps $100$ps $150$ps $350$ps $100$ps $100$ps And costs $($area associated with the number of transistors$)$: Inst. Mem. Adder Mux ALU Reg. file $($R$/$W$)$ Data Mem. Control Block Imm. Gen. $10005051002002000500300$ Consider the addition of a multiplier to the ALU. This addition will add $300$ps to the latency of the ALU and will add a cost of $600$ to the ALU. The result will be $10\%$ fewer instructions executed since we will no longer need to emulate the MUL instruction. $($Note: Ignore latencies and costs for components not mentioned here, such as PC and single gates.$)$ a$)$ What is the $($minimum$)$ clock cycle time with and without adding this new instruction? $(5$ points$)$ b$)$ What is the speedup achieved by adding this improvement? $(3$ points$)$ c$)$ Get the cost$/$relative$\_$performance ratio $($using the performance before the improvement as the referenced performance$)$ with and without this improvement and compare. From that point of view, do you recommend improvements? $(7$ points$)$