Write a VERILOG (verilog) code for 4 bit Booths algorithm using fsm and datapath. Details are below.

7.2 Datapath DesignTo achieve the signed binary number multiplication based on the Booths algorithm,datapath requires certain logic blocks including;three 4-bit registers to store and an arithmetic shiftrightM, A and Q values and a 1-bit register to store and anarithmetic shift rightQ-1value. An ALU will be used to perform arithmetic operations(A+M/A-M)and a down counter to keeptrack of the number of operationsof FSMbased on the number of bits that the datapath is designed for. This design should follow a parametric model so that the bit size of the multiplier can be adjusted. Firstly, use block diagram representation and design the datapath for Boots Algorithm, then write a parameterized Verilogcodeto defineyour datapath. Only 4-bit-user inputs(M and Q)are external inputs to the datapath and the CLK, RSTand the other control signals should come from the FSM.

7.3FSM DesignControl unit of this datapath will be implemented by the Booths_FSMas described in the lectures. The multiplier control FSM will have three external input START, CLK and RST. Once a Startsignal is received the Booth algorithm for multiplication processwill start and willcontinue until n(number of bits) in the down counter= 0.Add an asynchronous RSTsignal and out_statesignal to the design for debugging your FSM. FSM prepared in Experiment 6 can help you to implement Booths_FSM. Draw the state diagram for the FSMshowing all the inputs, outputs, and the state transitions clearly.