Question: You need to use this approach to do this additional problem, you can do it in the same Verilog file and test bench or separate

You need to use this approach to do this additional problem, you can do it in\ the same Verilog file and test bench or separate ones\ Create a Verilog expression for F\ Simplify to min SOP, justifying each step with the Boolean property used and call this Fs\ Create a testbench that tests all cases (there are 16)F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD

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