Question: (a) Consider a five-input CMOS NOR logic gate. Design the (W / L) ratios of the transistors to provide symmetrical switching times equal to the

(a) Consider a five-input CMOS NOR logic gate. Design the $W / L$ ratios of the transistors to provide symmetrical switching times equal to the basic CMOS inverter with $(W / L)_{n}=2$ and $(W / L)_{p}=4$.

(b) Repeat part (a) for a five-input CMOS NAND logic gate.

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