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Computer organization and architecture designing for performance 8th edition William stallings - Solutions

To get some feel for the effects of denormalization and gradual underflow, consider a decimal system that provides 6 decimal digits for the significand and for which the smallest normalized number is 10-99. A normalized number has one nonzero decimal digit to the left of the decimal point. Perform
Show how the following floating-point additions are performed (where significands are truncated to 4 decimal digits). Show the results in normalized form. a. 5.566 × 102 + 7.777 × 102 b. 3.344 × 101 + 8.877 × 10-2
Show how the following floating-point subtractions are performed (where significands are truncated to 4 decimal digits). Show the results in normalized form. a. 7.744 × 10-3 - 6.666 × 10-3 b. 8.844 × 10-3 - 2.233 × 10-1
Add columns to Table 9.1 for sign magnitude and ones complement.
Show how the following floating-point calculations are performed (where significands are truncated to 4 decimal digits). Show the results in normalized form. a. (2.255 × 101) × (1.234 × 100) b. (8.833 × 102) ÷ (5.555 × 104)
In Section 9.3, the twos complement operation is defined as follows. To find the twos complement of X, take the Boolean complement of each bit of X, and then add 1. a. Show that the following is an equivalent definition. For an n-bit integer X, the twos complement of X is formed by treating X as an
Calculate (72530 - 13250) using tens complement arithmetic. Assume rules similar to those for twos complement arithmetic.
Consider the twos complement addition of two n-bit numbers:zn-1zn-2 ... z0 = xn-1xn-2 ... x0 + yn-1yn-2 ... y0Assume that bitwise addition is performed with a carry bit ci generated by the addition of xi, yi, and ci-1. Let v be a binary variable indicating overflow when v = 1. Fill in the values in
What are the typical elements of a machine instruction?
What is the difference between big endian and little endian?
List and briefly explain five important instruction set design issues.
What is the relationship between the IRA character code and the packed decimal representation?
What is the difference between an arithmetic shift and a logical shift?
Why are transfer of control instructions needed?
List and briefly explain two common ways of generating the condition to be tested in a conditional branch instruction.
Suppose a stack is to be used by the processor to manage procedure calls and returns. Can the program counter be eliminated by using the top of the stack as a program counter? Discuss.
The x86 architecture includes an instruction called Decimal Adjust after Addition (DAA).DAA performs the following sequence of instructions: if ((AL AND 0FH) >9) OR (AF = 1) then AL ← AL + 6; AF ← 1; else AF ← 0; endif; if (AL > 9FH) OR (CF = 1) then AL ← AL + 60H; CF ← 1; else CF ←
The x86 Compare instruction (CMP) subtracts the source operand from the destination operand; it updates the status flags (C, P, A, Z, S, O) but does not alter either of the operands. The CMP instruction can be used to determine if the destination operand is greater than, equal to, or less than the
Suppose we wished to apply the x86 CMP instruction to 32-bit operands that contained numbers in a floating-point format. For correct results, what requirements have to be met in the following areas? a. The relative position of the significand, sign, and exponent fields. b. The representation of the
Many microprocessor instruction sets include an instruction that tests a condition and sets a destination operand if the condition is true. Examples include the SETcc on the x86, the Scc on the Motorola MC68000, and the Scond on the National NS32000.a. There are a few differences among these
Suppose that two registers contain the following hexadecimal values: AB0890C2, 4598EE50.What is the result of adding them using MMX instructions: a. For packed byte b. For packed word Assume saturation arithmetic is not used.
Convert the following formulas from reverse Polish to infix: a. AB + C + D × b. AB/CD/ + c. ABCDE + ××/ d. ABCDE + F/ + G - H/ ×+
Convert the following formulas from infix to reverse Polish: a. A + B + C + D + E h. (A + B) × (C + D) + E c. (A × B) + (C × D) + E d. (A - B) × (((C - D × E)/F)/G) × H
For each of the following packed decimal numbers, show the decimal value: a. 0111 0011 0000 1001 b. 0101 1000 0010 c. 0100 1010 0110
Using the algorithm for converting infix to postfix defined in Appendix 10A, show the steps involved in converting the expression of Figure 10.15 into postfix. Use a presentation similar to Figure 10.17.
Show the calculation of the expression in Figure 10.17, using a presentation similar to Figure 10.16.
Redraw the little-endian layout in Figure 10.18 so that the bytes appear as numbered in the big-endian layout. That is, show memory in 64-bit rows, with the bytes listed left to right, top to bottom.
For the following data structures, draw the big-endian and little-endian layouts, using the format of Figure 10.18, and comment on the results. a. struct { double i; //0x1112131415161718 } s1; b. struct { int i; //0x11121314 int j; //0x15161718 } s2; c. struct { short i; //0x1112 short j;
The IBM Power architecture specification does not dictate how a processor should implement little-endian mode. It specifies only the view of memory a processor must have when operating in little-endian mode. When converting a data structure from big endian to little endian, processors are free to
Write a small program to determine the endianness of machine and report the results. Run the program on a computer available to you and turn in the output.
Most, but not all, processors use big- or little-endian bit ordering within a byte that is consistent with big- or little-endian ordering of bytes within a multibyte scalar. Let us consider the Motorola 68030, which uses big-endian byte ordering. The documentation of the 68030 concerning formats is
A given microprocessor has words of 1 byte. What is the smallest and largest integer that can be represented in the following representations: a. Unsigned b. Sign-magnitude c. Ones complement d. Twos complement e. Unsigned packed decimal f. Signed packed decimal
Many processors provide logic for performing arithmetic on packed decimal numbers. Although the rules for decimal arithmetic are similar to those for binary operations, the decimal results may require some corrections to the individual digits if binary logic is used. Consider the decimal addition
The tens complement of the decimal number X is defined to be 10N - X, where N is the number of decimal digits in the number. Describe the use of ten's complement representation to perform decimal subtraction. Illustrate the procedure by subtracting (0326)10 - from (0736)10.
Compare zero-, one-, two-, and three-address machines by writing programs to computeX = (A + B Ã— C) / (D - E Ã— F)for each of the four machines. The instructions available for use are as follows:
Consider a hypothetical computer with an instruction set of only two n-bit instructions. The first bit specifies the opcode, and the remaining bits specify one of the 2n-1 n-bit words of main memory. The two instructions are as follows: SUBS X Subtract the contents of location X from the
Many instruction sets contain the instruction NOOP, meaning no operation, which has no effect on the processor state other than incrementing the program counter. Suggest some uses of this instruction.
In Section 10.4, it was stated that both an arithmetic left shift and a logical left shift correspond to a multiplication by 2 when there is no overflow, and if overflow occurs, arithmetic and logical left shift operations produce different results, but the arithmetic left shift retains the sign of
What facts go into determining the use of the addressing bits of an instruction?
What are the advantages and disadvantages of using a variable-length instruction format?
Briefly define displacement addressing.
What is the advantage of auto indexing?
What is the difference between post indexing and pre indexing?
Given the following memory values and a one-address machine with an accumulator, what values do the following instructions load into the accumulator? • Word 20 contains 40. • Word 30 contains 50. • Word 40 contains 60. • Word 50 contains 70. a. LOAD IMMEDIATE 20 b. LOAD DIRECT 20 c. LOAD
The x86 includes the following instruction: IMUL op1, op2, immediate This instruction multiplies op2, which may be either register or memory, by the immediate operand value, and places the result in op1, which must be a register. There is no other three-operand instruction of this sort in the
Define: EA = (X)+ is the effective address equal to the contents of location X, with X incremented by one word length after the effective address is calculated; is the effective address equal to the contents of location X, with X decremented by one word length before the effective address is
Assume a stack-oriented processor that includes the stack operations PUSH and POP. Arithmetic operations automatically involve the top one or two stack elements. Begin with an empty stack. What stack elements remain after the following instructions are executed? PUSH 4PUSH 7PUSH 8ADDPUSH 10SUBMUL
Why was IBM's decision to move from 36 bits to 32 bits per word wrenching, and to whom?
Assume an instruction set that uses a fixed 16-bit instruction length. Operand specifiers are 6 bits in length. There are K two-operand instructions and L zero-operand instructions. What is the maximum number of one-operand instructions that can be supported?
Design a variable-length opcode to allow all of the following to be encoded in a 36-bit instruction: • Instructions with two 15-bit addresses and one 3-bit register number • Instructions with one 15-bit address and one 3-bit register number • Instructions with no addresses or registers
Consider the results of Problem 10.6. Assume that M is a 16-bit memory address and that X, Y, and Z are either 16-bit addresses or 4-bit register numbers. The one-address machine uses an accumulator, and the two- and three-address machines have 16 registers and instructions operating on all
Is there any possible justification for an instruction with two opcodes?
Let the address stored in the program counter be designated by the symbol X1. The instruction stored in X1 has an address part (operand reference) X2. The operand needed to execute the instruction is stored in the memory word with address X3.An index register contains the value X4.What is the
The 16-bit Zilog Z8001 has the following general instruction format:The mode field specifies how to locate the operands from the operand fields. The w/b field is used in certain instructions to specify whether the operands are bytes or 16-bit words. The operand 1 field may (depending on the mode
An address field in an instruction contains decimal value 14. Where is the corresponding operand located for a. Immediate addressing? b. Direct addressing? c. Indirect addressing? d. Register addressing? e. Register indirect addressing?
Consider a 16-bit processor in which the following appears in main memory, starting at location 200:The first part of the first word indicates that this instruction loads a value into an accumulator. The Mode field specifies an addressing mode and, if appropriate, indicates a source register;
A PC-relative mode branch instruction is 3 bytes long. The address of the instruction, in decimal, is 256028. Determine the branch target address if the signed displacement in the instruction is -31.
A PC-relative mode branch instruction is stored in memory at address 62010. The branch is made to location 53010.The address field in the instruction is 10 bits long. What is the binary value in the instruction?
In [COOK82], the author proposes that the PC-relative addressing modes be eliminated in favor of other modes, such as the use of a stack. What is the disadvantage of this proposal?
What general roles are performed by processor registers?
What is the function of condition codes?
What is a program status word?
Why is a two-stage instruction pipeline unlikely to cut the instruction cycle time in half, compared with the use of no pipeline?
List and briefly explain various ways in which an instruction pipeline can deal with conditional branch instructions.
How are history bits used for branch prediction?
a. If the last operation performed on a computer with an 8-bit word was an addition in which the two operands were 00000010 and 00000011, what would be the value of the following flags? • Carry • Zero • Overflow • Sign • Even Parity • Half-Carry b. Repeat for the addition of (twos
A non pipelined processor has a clock rate of 2.5 GHz and an average CPI (cycles per instruction) of 4. An upgrade to the processor introduces a five-stage pipeline. However, due to internal pipeline delays, such as latch delay, the clock rate of the new processor has to be reduced to 2 GHz. a.
Consider an instruction sequence of length n that is streaming through the instruction pipeline. Let p be the probability of encountering a conditional or unconditional branch instruction, and let q be the probability that execution of a branch instruction I causes a jump to a nonconsecutive
One limitation of the multiple-stream approach to dealing with branches in a pipeline is that additional branches will be encountered before the first branch is resolved. Suggest two additional limitations or drawbacks.
Consider the state diagrams of Figure 12.28.a. Describe the behavior of each.b. Compare these with the branch prediction state diagram in Section 12.4. Discuss the relative merits of each of the three approaches to branch prediction.Figure 12.28 Two Branch Prediction State Diagrams
The Motorola 680x0 machines include the instruction Decrement and Branch According to Condition, which has the following form: DBcc Dn, displacement where cc is one of the testable conditions, Dn is a general-purpose register, and displacement specifies the target address relative to the current
Redraw Figures 12.19c, assuming that the conditional branch is not taken.Figure 12.19 Branch Prediction State Diagram
Table 12.5 summarizes statistics from [MACD84] concerning branch behavior for various classes of applications. With the exception of type 1 branch behavior, there is no noticeable difference among the application classes. Determine the fraction of all branches that go to the branch target address
Pipelining can be applied within the ALU to speed up floating-point operations. Consider the case of floating-point addition and subtraction. In simplified terms, the pipeline could have four stages: (1) Compare the exponents; (2) Choose the exponent and align the significands; (3) Add or subtract
Repeat Problem 12.1 for the operation A B, where A contains 11110000 and B contains 0010100.
A microprocessor provides an instruction capable of moving a string of bytes from one area of memory to another. The fetching and initial decoding of the instruction takes 10 clock cycles. Thereafter, it takes 15 clock cycles to transfer each byte. The microprocessor is clocked at a rate of 10
Assume an 8088 is executing a program in which the probability of a program jump is 0.1. For simplicity, assume that all instructions are 2 bytes long. a. What fraction of instruction fetch bus cycles is wasted? b. Repeat if the instruction queue is 8 bytes long.
Consider the timing diagram of Figures 12.10. Assume that there is only a two-stage pipeline (fetch, execute). Redraw the diagram to show how many time units are now needed for four instructions.Figure 12.10 Timing Diagram for Instruction Pipeline Operation
Assume a pipeline with four stages: fetch instruction (FI), decode instruction and calculate addresses (DA), fetch operand (FO), and execute (EX). Draw a diagram similar to Figures 12.10 for a sequence of 7 instructions, in which the third instruction is a branch that is taken and in which there
A pipelined processor has a clock rate of 2.5 GHz and executes a program with 1.5 million instructions. The pipeline has five stages, and instructions are issued at a rate of one per clock cycle. Ignore penalties due to branch instructions and out of sequence executions. a. What is the speedup of
What are some typical distinguishing characteristics of RISC organization?
Briefly explain the two basic approaches used to minimize register-memory operations on RISC machines.
If a circular register buffer is used to handle local variables for nested procedures, describe two approaches for handling global variables.
Considering the call-return pattern, how many overflows and underflows (each of which causes a register save/restore) will occur with a window size of a. 5? b. 8? c. 16?
SPARC is lacking a number of instructions commonly found on CISC machines. Some of these are easily simulated using either register R0, which is always set to 0, or a constant operand. These simulated instructions are called pseudo instructions and are recognized by the SPARC compiler. Show how to
Consider the following code fragment:if K > 10L: = K + 1elseL: = K - 1;A straightforward translation of this statement into SPARC assembler could take the following form:The code contains a nop after each branch instruction to permit delayed branch operation. a. Standard compiler optimizations that
We wish to determine the execution time for a given program using the various pipelining schemes discussed in Section 13.5. Let N = number of executed instructions D = number of memory accesses J = number of jump instructions For the simple sequential scheme (Figure 13.6a), the execution time is
Reorganize the code sequence in Figure 13.6d to reduce the number of NOOPs.Figure 13.6d
Consider the following code fragment in a high-level language:Assume that Q is an array of 32-byte records and the VAL field is in the first 4 bytes of each record. Using x86 code, we can compile this program fragment as follows: This program makes use of the IMUL instruction, which multiplies the
Consider the following loop:S: = 0;for K: = 1 to 100 doS: = S - K;A straightforward translation of this into a generic assembly language would look something like this:A compiler for a RISC machine will introduce delay slots into this code so that the processor can employ the delayed branch
A RISC machine may do both a mapping of symbolic registers to actual registers and a rearrangement of instructions for pipeline efficiency. An interesting question arises as to the order in which these two operations should be done. Consider the following program fragment:a. First do the register
Add entries for the following processors to Table 13.7:Table 13.7 Characteristics of Some Processorsa. Pentium IIb. ARM
In many cases, common machine instructions that are not listed as part of the MIPS instruction set can be synthesized with a single MIPS instruction. Show this for the following: a. Register-to-register move b. Increment, decrement c. Complement d. Negate e. Clear
What is the essential characteristic of the superscalar approach to processor design?
What is the difference between the superscalar and super pipelined approaches?
Briefly define the following terms: • True data dependency • Procedural dependency • Resource conflicts • Output dependency • Ant dependency
What is the distinction between instruction-level parallelism and machine parallelism?
List and briefly define three types of superscalar instruction issue policies.
What is register renaming and what is its purpose?
What are the key elements of a superscalar processor organization?

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