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computer sciences
systems analysis and design

Questions and Answers of Systems Analysis And Design

What, in general terms, is the distinction between computer structure and computer function?
List and briefly define the main structural components of a computer.
List and briefly define the main structural components of a processor.
What is a stored program computer?
What are the four main components of any general-purpose computer?
Explain Moore's law.
List and explain the key characteristics of a computer family.
Let A = A(1), A(2), . . . , A(1000) and B = B(1), B(2), . . . , B(1000) be two vectors (one-dimensional arrays) comprising 1000 numbers each that are to be added to form an array C such that C(I) =
Consider two different machines, with two different instruction sets, both of which have a clock rate of 200 MHz. The following measurements are recorded on the two machines running a given set of
Early examples of CISC and RISC design are the VAX 11/780 and the IBM RS/6000, respectively. Using a typical benchmark program, the following machine characteristics result:The final column shows
Four benchmark programs are executed on three computers with the following results:The table shows the execution time in seconds, with 100,000,000 instructions executed in each of the four programs.
The following table, based on data reported in the literature [HEAT84], shows the execution times, in seconds, for five different benchmark programs on three machines.a. Compute the speed metric for
To clarify the results of the preceding problem, we look at a simpler example.a. Compute the arithmetic mean value for each system using X as the reference machine and then using Y as the reference
Consider the example in Section 2.5 for the calculation of average CPI and MIPS rate, which yielded the result of CPI = 2.24 and MIPS rate = 178. Now assume that the program can be executed in eight
A processor accesses main memory with an average access time of T2. A smaller cache memory is interposed between the processor and main memory. The cache has a significantly faster access time of T1
a. On the IAS, what would the machine code instruction look like to load the contents of memory address 2? b. How many trips to memory does the CPU need to make to complete this instruction during
On the IAS, describe in English the process that the CPU must undertake to read a value from memory and to write a value to memory in terms of what is put into the MAR, MBR, address bus, data bus,
Given the memory contents of the IAS computer shown below, Address Contents 08A .......... 010FA210FB 08B .......... 010FA0F08D 08C .......... 020FA210FB show the assembly language code for the
In the IBM 360 Models 65 and 75, addresses are staggered in two separate main memory units (e.g., all even-numbered words in one unit and all odd-numbered words in another).What might be the purpose
With reference to Table 2.4, we see that the relative performance of the IBM 360 Model 75 is 50 times that of the 360 Model 30, yet the instruction cycle time is only 5 times as fast. How do you
While browsing at Billy Bob's computer store, you overhear a customer asking Billy Bob what is the fastest computer in the store that he can buy. Billy Bob replies, "You're looking at our
The ENIAC was a decimal machine, where a register was represented by a ring of 10 vacuum tubes. At any time, only one vacuum tube was in the ON state, representing one of the 10 digits. Assuming that
What general categories of functions are specified by computer instructions?
List and briefly define the possible states that define an instruction execution.
List and briefly define two approaches to dealing with multiple interrupts.
What types of transfers must a computer's interconnection structure (e.g., bus) support?
List and briefly define the functional groups of signal lines for PCI.
The hypothetical machine of Figure 3.4 also has two I/O instructions:0011 = Load AC from I/O0011 = Store AC to I/OIn these cases, the 12-bit address identifies a particular I/O device. Show the
On the VAX SBI, the lowest-priority device usually has the lowest average wait time. For this reason, the processor is usually given the lowest priority on the SBI. Why does the priority 16 device
For a synchronous read operation (Figure 3.19), the memory module must place the data on the bus sufficiently ahead of the falling edge of the Read signal to allow for signal settling. Assume a
Consider a microprocessor that has a memory read timing as shown in Figure 3.19. After some analysis, a designer determines that the memory falls short of providing read data on time by about 180
A microprocessor has a memory write timing as shown in Figure 3.19. Its manufacturer specifies that the width of the Write signal can be determined by T - 50, where T is the clock period in ns.a.
A microprocessor has an increment memory direct instruction, which adds 1 to the value in a memory location. The instruction has five stages: fetch opcode (four bus clock cycles), fetch operand
The Intel 8088 microprocessor has a read bus timing similar to that of Figure 3.19, but requires four processor clock cycles. The valid data is on the bus for an amount of time that extends into the
The Intel 8086 is a 16-bit processor similar in many ways to the 8-bit 8088. The 8086 uses a 16-bit bus that can transfer 2 bytes at a time, provided that the lower-order byte has an even address.
Consider a 32-bit microprocessor whose bus cycle is the same duration as that of a 16-bit microprocessor. Assume that, on average, 20% of the operands and instructions are 32 bits long, 40% are 16
Draw and explain a timing diagram for a PCI write operation.
The program execution of Figure 3.5 is described in the text using six steps. Expand this description to show the use of the MAR and MBR.
Consider a hypothetical 32-bit microprocessor having 32-bit instructions composed of two fields: the first byte contains the opcode and the remainder the immediate operand or an operand address. a.
Consider a hypothetical microprocessor generating a 16-bit address (for example, assume that the program counter and the address registers are 16 bits wide) and having a 16-bit data bus. a. What is
Consider a 32-bit microprocessor, with a 16-bit external data bus, driven by an 8-MHz input clock. Assume that this microprocessor has a bus cycle whose minimum duration equals four input clock
Consider a computer system that contains an I/O module controlling a simple keyboard/printer teletype. The following registers are contained in the processor and connected directly to the system
Consider two microprocessors having 8- and 16-bit-wide external data buses, respectively. The two processors are identical otherwise and their bus cycles take just as long. a. Suppose all
Figure 3.26 indicates a distributed arbitration scheme that can be used with an obsolete bus scheme known as Multibus I. Agents are daisy-chained physically in priority order. The left-most agent in
What are the differences among sequential access, direct access, and random access?
How does the principle of locality relate to the use of multiple memory levels?
What are the differences among direct mapping, associative mapping, and set-associative mapping?
For a direct-mapped cache, a main memory address is viewed as consisting of three fields. List and define the three fields.
For a set-associative cache, a main memory address is viewed as consisting of three fields. List and define the three fields.
What is the distinction between spatial locality and temporal locality?
In general, what are the strategies for exploiting spatial locality and temporal locality? Discuss.
A set-associative cache consists of 64 lines, or slots, divided into four-line sets. Main memory contains 4K blocks of 128 words each. Show the format of main memory addresses.
A set-associative cache consists of 64 lines, or slots, divided into four-line sets. Main memory contains 4K blocks of 128 words each. Show the format of main memory addresses. Discuss.
A set-associative cache has a block size of four 16-bit words and a set size of 2. The cache can accommodate a total of 4096 words. The main memory size that is cacheable is 64K 32 bits. Design the
Consider a memory system that uses a 32-bit address to address at the byte level, plus a cache that uses a 64-byte line size. a. Assume a direct mapped cache with a tag field in the address of 20
Consider a computer with the following characteristics: total of 1Mbyte of main memory; word size of 1 byte; block size of 16 bytes; and cache size of 64 Kbytes. a. For the main memory addresses of
Describe a simple technique for implementing an LRU replacement algorithm in a four-way set-associative cache.
Consider again Example 4.3. How does the answer change if the main memory uses a block transfer capability that has a first-word access time of 30 ns and an access time of 5 ns for each word
Consider the following code: for (i = 0; i < 20; i++) for ( j = 0; j < 10; j++) a[i] = a[i]* j a. Give one example of the spatial locality in the code. b. Give one example of the temporal locality in
Generalize Equations (4.2) and (4.3), in Appendix 4A, to N-level memory hierarchies.Equations (4.2)Ts = H Ã— T1 + (1 - H) Ã— (T1 + T2)= T1 + (1 - H) Ã— T2Equations (4.3)
A computer system contains a main memory of 32K 16-bit words. It also has a 4Kword cache divided into four-line sets with 64 words per line. Assume that the cache is initially empty. The processor
Consider a cache of 4 lines of 16 bytes each. Main memory is divided into blocks of 16 bytes each. That is, block 0 has bytes with addresses 0 through 15, and so on. Now consider a program that
Consider a memory system with the following parameters: Tc = 100 ns Cc = 10-4 $/bit Tm = 1200 ns Cm = 10-5 $/bit a. What is the cost of 1 Mbyte of main memory? b. What is the cost of 1 Mbyte of main
A two-way set-associative cache has lines of 16 bytes and a total size of 8 kbytes. The 64-Mbyte main memory is byte addressable. Show the format of main memory addresses.
a. Consider an L1 cache with an access time of 1 ns and a hit ratio of H = 0.95. Suppose that we can change the cache design (size of cache, cache organization) such that we increase H to 0.97, but
Consider a single-level cache with an access time of 2.5 ns, a line size of 64 bytes, and a hit ratio of H = 0.95. Main memory uses a block transfer capability that has a first-word (4 bytes) access
A computer has a cache, main memory, and a disk used for virtual memory. If a referenced word is in the cache, 20 ns are required to access it. If it is in main memory but not in the cache, 60 ns are
Consider a cache with a line size of 64 bytes. Assume that on average 30% of the lines in the cache are dirty. A word consists of 8 bytes. a. Assume there is a 3% miss rate (0.97 hit ratio). Compute
On the Motorola 68020 microprocessor, a cache access takes two clock cycles. Data access from main memory over the bus to the processor takes three clock cycles in the case of no wait state
Assume a processor having a memory cycle time of 300 ns and an instruction processing rate of 1 MIPS. On average, each instruction requires one bus memory cycle for instruction fetch and one for the
The performance of a single-level cache system for a read operation can be characterized by the following equation: Ta = Tc + (1 - H)Tm where Ta is the average access time, Tc is the cache access
Assume the following performance characteristics on a cache read miss: one clock cycle to send an address to main memory and four clock cycles to access a 32-bit word from main memory and transfer it
For the cache design of the preceding problem, suppose that increasing the line size from one word to four words results in a decrease of the read miss rate from 3.2% to 1.1%. For both the non burst
For the hexadecimal main memory addresses 111111, 666666,BBBBBB, show the following information, in hexadecimal format:a. Tag, Line, and Word values for a direct-mapped cache, using the format of
List the following values: a. For the direct cache example of Figure 4.10: address length, number of addressable units, block size, number of blocks in main memory, number of lines in cache, size of
Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associative cache. Assume that the cache has a line size of four 32-bit words. Draw a block diagram of this cache showing
Given the following specifications for an external cache memory: four-way set associative; line size of two 16-bit words; able to accommodate a total of 4K 32-bit words from main memory; used with a
Consider a machine with a byte addressable main memory of 216 bytes and block size of 8 bytes. Assume that a direct mapped cache consisting of 32 lines is used with this machine. a. How is a 16-bit
For its on-chip cache, the Intel 80486 uses a replacement algorithm referred to as pseudo least recently used. Associated with each of the 128 sets of four lines (labeled L0, L1, L2, L3) are three
What are the key properties of semiconductor memory?
How is the syndrome for the Hamming code interpreted?
How does SDRAM differ from ordinary DRAM?
What are two senses in which the term random-access memory is used?
Explain why one type of RAM is considered to be analog and the other digital.
What are the differences among EPROM, EEPROM, and flash memory?
Explain the function of each pin in Figure 5.4b.Figure 5.4b
Suggest reasons why RAMs traditionally have been organized as only 1 bit per chip whereas ROMs are usually organized with multiple bits per chip.
For the Hamming code shown in Figure 5.10, show what happens when a check bit rather than a data bit is in error?
Suppose an 8-bit data word stored in memory is 11000010. Using the Hamming algorithm, determine what check bits would be stored in memory with the data word. Show how you got your answer.
For the 8-bit word 00111001, the check bits stored with it would be 0111. Suppose when the word is read from memory, the check bits are calculated to be 1101.What is the data word that was read from
Develop an SEC code for a 16-bit data word. Generate the code for the data word 0101000000111001. Show that the code will correctly identify an error in data bit 5.
Consider a dynamic RAM that must be given a refresh cycle 64 times per ms. Each refresh operation requires 150 ns; a memory cycle requires 250 ns. What percentage of the memory's total operating time
Figure 5.16 shows a simplified timing diagram for a DRAM read operation over a bus. The access time is considered to last from t1 to t2. Then there is a recharge time, lasting from t2 to t3, during
Figure 5.6 indicates how to construct a module of chips that can store 1 MByte based on a group of four 256-Kbyte chips. Let's say this module of chips is packaged as a single 1-Mbyte chip, where the
On a typical Intel 8086-based system, connected via system bus to DRAM memory, for a read operation, is activated by the trailing edge of the Address Enable signal (Figure 3.19). However, due to
The memory of a particular microcomputer is built from 64K × 1 DRAMs. According to the data sheet, the cell array of the DRAM is organized into 256 rows. Each row must be refreshed at least once
Figure 5.17 shows one of the early SRAMs, the 16 Ã— 4 Signetics 7489 chip, which stores 16 4-bit words.a. List the mode of operation of the chip for each input pulse shown in Figure
Design a 16-bit memory of total capacity 8192 bits using SRAM chips of size 64 × 1 bit. Give the array configuration of the chips on the memory board showing all required input and output signals
A common unit of measure for failure rates of electronic components is the Failure unIT (FIT), expressed as a rate of failures per billion device hours. Another well known but less used measure is
What are the advantages of using a glass substrate for a magnetic disk?

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