Questions and Answers of Computer Architecture

Calculate the theoretical maximum capacity of a single-layer Blu-ray disk, assuming that a single laser spot can burn a 1 or 0 and that the wavelength of the laser is 405 nm, the numerical aperture
Why are there no RAID systems using optical memory?
What are the relative advantages and disadvantages of SSDs and HDDs?
A peripheral interface chip may have several internal registers. Explain the techniques available to reduce the number of address lines required to access these registers. Can you think of any
A computer with interrupt-driven I/0 has an interrupt response time of 4 µ,s (i. e., it takes 4 µ,s to invoke the interrupt handler and begin executing the target code). Similarly, it takes 2 µ,s
A computer spends 80% of its time executing user code and 20% of its time performing input/output operations. If you regard I/0 as an unn ecessary overhead, the efficiency of the computer is 80/(80 +
An I/0 system using DMA has a latency time of 10 ms between the peripheral requesting a data transfer and the transfer beginning. This system transfers data at the rate of one byte per µ,s. What is
This question asks you about the way in which the performance of I/0 systems has changed and requires you to carry out your own research. Plot the maximum speed per data transfer as a function of
If Ethernet addresses were uniformly distributed among all the people on the planet, would there be enough address space for each human? If there is more than one address per person, how many add
An interrupt-based I/0 system uses polled interrupt handling where the processor has to interrogate each peripheral's interrupt status flag after an interrupt request. Suppose that an interrupt
What are the relative merits of open-loop and closed-loop data transfers? What factors would you take into account if you had to choose one over the other for a specific application?
A high-speed USB 2.0 port uses 30% of the available bandwidth. The bus is used to read a flash card with 700 images-each consisting of 25 MB. If the card is not the limiting factor, how long does it
In what ways is the USB bus better than the RS232C bus?
A microprocessor has a prioritized vectored interrupt handling mechanism. In this context, what are the meanings of the two words in italics?
Can the interrupt handling system make a computer more vulnerable to the dangers of malware ( e.g., a virus)? If so, how and why?
Suppose you were designing a special-purpose 1/0 chip to relieve a high-performance workstation of the burden of 1/0. What special instructions would you add to the computer's instruction set? What
Why is double-buffered input sometimes required?
Under what circumstances is a FIFO necessary in an 1/0 environment?
Figure P12.19 gives the timing diagram of the IEEE 488 bus's data transfer. This bus was first designed for use in an intelligent automated instrumentation (laboratory) environment. Multiple
The clocked circuit in Figure P12.20 is an arbiter. Suppose two devices, 1 and 2, can request a resource such as a bus at any instant. The problem is to ensure that only one requester is granted the
An application is 80% computation intensive and takes up 60% of a computer's capacity (both CPU and 1/0). Assume that this application will demand 20% more resources each year as it is updated; the
Why did IBM's Microchannel architecture fail commercially?
What is a split-transaction in the context of 1/0, and when may it be necessary?
You have a system that transmits data between two points in packets of 1024 bytes. The transmitted bit rate is 10 Mbps. Before a packet is transmitted, a handshake must take place with the recipient,
What is the difference between distributed arbitration and centralized arbitration?
A bus has a characteristic impedance of 75 Ω. It is terminated by a resistance of 200 Ω. What is the reflection coefficient at the termination?
What is an atomic or indivisible operation ( or instruction), and why is it necessary?
Why is the machine status saved during an interrupt call and not during a subroutine call?
A computer has an average interrupt response time of p, takes q to process an interrupt, and takes s to return from interrupt. If a polled interrupt mechanism is implemented and takes x to poll a
Why do superscalar processors present a particular problem when implementing memory-mapped 1/0. How can that problem be overcome?
Memory-mapped I/0 may fail to operate in a system with cache memory. Why? What is the remedy?
What is a nested interrupt? What are the advantages and disadvantages of nested interrupts?
Does the Ethernet physical layer protocol represent an open- or closed-loop operation?
Parallel processing-why here, why now? For a long time, parallel processing was an esoteric graduate-level topic. Suddenly, it became mainstream. Explain why this has happened.
If the Earth's atmosphere is considered to extend from the surface to 20 km, the earth's radius is 6,200 km, and the atmosphere is partitioned into cells spaced 0.5 km apart, how many floating-point
Does parallel processing in the form of multi-core processors represent the future ... or the past?
Is Amdahl's law a friend or foe of parallel processing?
A multiprocessor computer can execute a program using multiple processors. If the problem can be divided into parts that can run on the following number of processors, what is the speedup? Number
For the MESI protocol, fill in the next state for each of the entries in the following table. that some entries are not possible and can be left empty. Current state of line / in cache of processorj
A write-back of data occurs from only one state in the MESI protocol. Which state is that?
What is the advantage of the E (exclusive) state in the 4-state MESI protocol over the 3-state MSI protocol?
Is an n-core multiprocessor n times as fast as the equivalent single core microprocessor? Give your reasoning.
What, if any, is the difference between a multi-core processor and a co-processor?
What is false sharing in a multiprocessor system, and how does it affect performance?
What is the difference between a multi-core processor and a GPU?
A program is ported from a single-core processor to a dual core processor and open MPI used to parallelize it. It runs more slowly on the dual-core processor than on the single-core processor. Why?
The following six topics are associated with OpenMP or MPI. Indicate which is which. • Message passing between processes • Shared memory • Distributed memory • Does not run on
Where do you think the bottlenecks (limitations or barriers) to the growth of the computer (in terms of its computational power and its abilities/application) lie?
Is Moore's law a law?
Why do you think that Moore's law 'exists'? What drives it or makes it possible?
Why is binary arithmetic employed by digital computers?
We said that binary values have no intrinsic information (that is true of all other number representations). The Voyager I spacecraft, containing samples of human music and other messages, was the
How much more inaccurate is binary integer arithmetic than decimal integer arithmetic? Can the accuracy of binary computers be improved to make them as accurate as decimal computers?
Why are computers byte-oriented?
Calculations are to be performed to a precision of 0.001 %. How many bits does this require?
What are the decimal equivalents of the following values (assume positional notation and unsigned integer formats)? a. 11001100 c. 110011004 b. 110011003 d. 11001100_2
Why do we have octal and hexadecimal arithmetic?
Convert the following decimal numbers into ( a) binary and (b) hexadecimal forms. a. 25 c. 2500 b. 250 d. 25555
Convert the following unsigned binary numbers into decimal form. a. 11 c. 10001 b. 1001 d. 10011001
Convert the follow ing hexadecimal numbers into decimal form. a. AB c. 10A01 b. A0B d. FFAAFF
Convert the following binary format. a. AC c. 10B11 b. DFOB d. FDEAF1
Convert the following fractional decimal numbers into 16-bit unsigned binary form. Use eight bits of precision. a. 0.2 c. 0.1111 b. 0.046875 d. 0.1234
Perform the following calculations in the stated bases. a. 001101112 +010110112 C. 0012012116 +0A01503116 b. 001111112 +01001001 d. 00ABCD1F16 + 0F00 800 F16
What is arithmetic overflow? When does it occur and how can it be detected?
Then-bit two's complement integer N is written an-1, an-2, ,,, a1, a0• Prove that (in two's complement notation) the representation of a signed binary number in n + 1 bits may be derived from its
Convert 1234.125 into 32-bit IEEE floating-point format.
What is the decimal equivalent of the 32-bit IEEE floating-point value CC4C0000?
What is the difference between overflow in the context of two's complement numbers and overflow in the context of floating-point numbers?
In the negabinary system an i-bit binary integer, N, is expressed using positional notation as:This is the same as conventional natural 8421 binary weighted numbers, except that alternate positions
Perform the following additions on 4-bit negabinary numbers. The result is a 6-bit negabinary value. a. 0000 +0001 c. 1101 1011 b. 1010 +0101 d. 1111 1111
Arithmetic overflow occurs during a two's complement addition if the result of adding two positive numbers yields a negative result or if adding two negative numbers yields a positive result. If the
What is the difference between a truncation error and a rounding error?
Positive and negative numbers can be represented in many ways in a computer. List some of the ways of representing signed numbers. Can you think of any other ways of representing signed values?
What is a NaN and what is its significance in floatingpoint arithmetic?
What is the largest three-digit number in base 13?
You are evaluating x2 - y2 where x = 12.1234 and y = 12.1111. If arithmetic operations are carried out to six significant figures (in decimal), does it matter whether you evaluate this expression as
You are evaluating the function x4 + 4x2 + 10x + 2 at x = 2. What is the estimated error if the error in x is Rx?
What does the following ASCII-encoded message mean? Each character is given in hexadecimal form. 43, 6F, 6D, 70, 75, 74, 65, 72, 2E
Floating-point arithmetic is seldom used to perform financial calculations. Why?
Modern computers use unsigned integer arithmetic, fixed-point arithmetic, two's complement arithmetic, and floating-point arithmetic. a. By examining a binary number, can you tell which number
For each for the following numbers, state the base in use; that is, what is p, q, r, s, t, u? a. 100001, = 3310 b. 25 = 1310 c. 25, = 2310 d. 25, = 3710 e. 1010, 6810 f. 1001, = 12610
A digital logic element represents the high state with an output of between 2.8 and 2.95 V. The same logic element will see an input high state as a voltage in the range of 2.1 to 3.0 V. What is the
Draw a truth table to represent the intermediate values and output of the circuit in Figure P2.34. FIGURE P2.34 A B D F
In a digital system, what is the meaning of negative logic?
The signal RESET is asserted. What does this statement mean?
A digital system has four one-bit inputs D, C, B, A and an output F. The input represents a 4-bit number in the range of O through 15, where A denotes the least-significant bit. The output Fis true
Consider the circuit in Figure P2.38 that takes a 4-bit binary input and encodes it. Construct a truth table for the 16 inputs 0000 to 1111 and examine the output code. What is the characteristic
A logic circuit has two 2-bit natural binary inputs A and B. A is given by A1, A0, where A1 is the most significant bit. Similarly, Bis given by B1, B0, where B1 is the most-significant bit. The
Draw a truth table for the circuit in Figure P2.40 and explain what it does. FIGURE P2.30 A B P R C
The circuit in Figure P2.41 receives three pairs of inputs a0, b0, a1, b1, ,,, , a3, b3 and produces a 4-bit output c0, c1, ,,, , c3. Analyze the circuit and explain what it does in plain English.
Demonstrate that all logic circuits can be constructed from NOR gates by building an inverter, an AND gate, and an OR gate from one or more NOR gates.
Design a logic circuit to implement the logical function X = ABC + A.B.C
Simplify the following Boolean expressions. a. F= A.B.C.D + ABCD + ABCD + A.B.C.D b. F= A.B.C + ABC + ACD + AB.C.D c. F = ACD + ABCD + A.B.C
It is possible to haven-input AND, OR, NAND, and NOR gates, where n > 2. Can you have an n-input XOR gate for n > 2? Explain your answer with a truth table.
Design a D flip-flop using only an RS latch and simple gates. Include a circuit diagram, timing diagram, and truth table in your answer.
Without the tristate gate, it would be almost impossible to design a modern computer. Why is this so?
The circuit in Figure P2.49 consists of four JK flip-flops. Inputs J and K are not shown, because it is assumed that they are both permanently connected to a logical 1. These JK flip-flops are
Consider the circuit in Figure P2.50. Assume that all gates are implemented in silicon by NANO gates, NOR gates and inverters. Each NANO gate, NOR gate, or inverter has an internal delay of 0.4 ns. A
The state diagram in Figure P2.51 describes a system with states A, B, and C. The system is initialized in State A. The state transition notation x/yz indicates that an input x causes a transition in
The structure in Figure P2.52 contains registers, ALUs, multiplexers, tristate gates, and buses and is essentially a more elaborate form of the register, ALU structure we introduced in this chapter.

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