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Computer Organization And Architecture Themes And Variations 1st Edition Alan Clements - Solutions

The signal RESET is asserted. What does this statement mean?
A digital system has four one-bit inputs D, C, B, A and an output F. The input represents a 4-bit number in the range of O through 15, where A denotes the least-significant bit. The output Fis true if the binary input is divisible by 3, 4, or 7. Construct a truth table to represent this system and
Consider the circuit in Figure P2.38 that takes a 4-bit binary input and encodes it. Construct a truth table for the 16 inputs 0000 to 1111 and examine the output code. What is the characteristic feature of this code? FIGURE P2.38 b4 94 8421 binary input b2 b3 93 b 92 Encoded output 91 bo 90
A logic circuit has two 2-bit natural binary inputs A and B. A is given by A1, A0, where A1 is the most significant bit. Similarly, Bis given by B1, B0, where B1 is the most-significant bit. The circuit has three outputs, X, Y, and Z. This circuit compares A with B and determines whether A is
Draw a truth table for the circuit in Figure P2.40 and explain what it does. FIGURE P2.30 A B P R C
The circuit in Figure P2.41 receives three pairs of inputs a0, b0, a1, b1, ,,, , a3, b3 and produces a 4-bit output c0, c1, ,,, , c3. Analyze the circuit and explain what it does in plain English. FIGURE P2.34 ao bo a1 b1 89 a2 b2 5. b3 X1 X2 X3 CO C1 C2 C3
Demonstrate that all logic circuits can be constructed from NOR gates by building an inverter, an AND gate, and an OR gate from one or more NOR gates.
Design a logic circuit to implement the logical function X = ABC + A.B.C
Simplify the following Boolean expressions. a. F= A.B.C.D + ABCD + ABCD + A.B.C.D b. F= A.B.C + ABC + ACD + AB.C.D c. F = ACD + ABCD + A.B.C
It is possible to haven-input AND, OR, NAND, and NOR gates, where n > 2. Can you have an n-input XOR gate for n > 2? Explain your answer with a truth table.
Design a D flip-flop using only an RS latch and simple gates. Include a circuit diagram, timing diagram, and truth table in your answer.
Without the tristate gate, it would be almost impossible to design a modern computer. Why is this so?
The circuit in Figure P2.49 consists of four JK flip-flops. Inputs J and K are not shown, because it is assumed that they are both permanently connected to a logical 1. These JK flip-flops are positive edge-triggered (i.e., they change state on the rising edge of the clock). Note that these
Consider the circuit in Figure P2.50. Assume that all gates are implemented in silicon by NANO gates, NOR gates and inverters. Each NANO gate, NOR gate, or inverter has an internal delay of 0.4 ns. A logic transition at an input may cause a change at the output ( depending on other inputs and the
The state diagram in Figure P2.51 describes a system with states A, B, and C. The system is initialized in State A. The state transition notation x/yz indicates that an input x causes a transition in the direction shown and the system outputs the value yz. For example, an input 1 in State A causes
The structure in Figure P2.52 contains registers, ALUs, multiplexers, tristate gates, and buses and is essentially a more elaborate form of the register, ALU structure we introduced in this chapter. As a computing structure, what are the advantages of this over the simpler system we described
Why is the program counter a pointer and not a counter?
Explain the function of the following registers in a CPU. a. PC b. MAR C. MBR d. IR
For each of the following 6-bit operations, calculate the values of the C, Z, V, and N flags. a. 001011 +001101 d. 101101 +011011 b. 111111 +000001 e. 000000 -000001 c. 000000 -111111 f. 111110 +111111
The classic processors flags are C, N, V , and Z. Conditional branches may be made on these flags be ing true or false (branch on zero or not zero). Branches may be on combinations of flags (branch on greater than or equal to zero). Can you think of any other conditional branch conditions that
The ARM's r13 and r14 registers are overlapped (banked or windowed), and a separate register pair exists for each of the exception modes. What do we mean when we say these registers are overlapped? Explain why the ARM's designers have taken this approach.
ARM's literature often describes its assembly language instruction syntax in BNF notation. Suppose an instruction is described in BNF as having the syntax: Give examples of possible legal instructions using this format. This That {B} {S} {,P|Q}
The ARM puts the program counter in register r15, making it visible to the programmer. Someone writing about the ARM stated that this exposed the ARM's pipeline. What did he mean, and why? Note: You may have to look at the section o n pipelining to answer this.
What are the relative advantages and disadvantages of general-purpose registers compared to separate address and data registers?
What is a misaligned operand? Why are misaligned operands such a problem in programming?
If rl = 0FFF16 and r2 = 4, what is the value of r3 after each of the following instructions has been executed ( assume that each instruction uses the same data) ? a. MOV r3, rl, b. MOV r3, rl, c. MVN r3, rl, d. MVN r3, rl, LSL r2 LSR r2 LSL r2 LSR r2
If rl = 00FF16 and r2 = 4, what is the value of r0 after each of the following instructions has been executed (assume that each instruction uses the same data)? a. ADD r0, rl, rl, b. ADD r0, rl, rl, c. ADD r0, rl, rl, LSL #2 LSL #4 ROR #4
Write an ARM assembly language routine to count the number of ls in a 32-bit word in r0 and return the result in rl.
A word consists of the bytes b4, b3, b2, and bl. Write a function to re-order (transpose) these bytes in the order bl, b3, b2, and b4.
ARM instructions have a 12-bit literal. Instead of permitting a word in the range 0 to 212 - 1, the ARM uses an 8-bit format for the integer and a 4-bit alignment field that allows the integer to be shifted in steps of 2. What are the advantages and disadvantages of this mechanism in comparison
Write one or more ARM instructions that will clear bits 20 to 25 inclusive in register r0. All the other bits of r0 should remain unchanged.
This is a classic problem of assembly language programming. Write a sequence of ARM instructions that swap the contents of registers r0 and rl without using any additional registers or memory storage (that is, you can't move rl to a temporary location).
What is the difference between the TEQ and CMP and CMN comparison instructions?
What are the advantages and disadvantages of the use of the ARM's BL (branch and load) subroutine call mechanism in comparison with the conventional CISC BSR (branch to subroutine) mechanism?
Write ARM code to implement the following C operation. int s = 0; for (i = 0; i < 10; i++) { S = s + i*i;)
What is the effect of the following addressing mode? STR r0, [r2, r3, ROR #3] !
What is the meaning of each of the P, U, B, W, and L bits in the encoding of an ARM memory reference instruction?
What is the binary encoding of the following instructions? a. STRB b. LDR c. LDR d. LDR r1, [r2] r3, [r4, r5] ! r3, [r4], r5 r3, [r4 , #-6] !
What is the effect of LDR rO, [r5, r6, LSL r2]?
You go for a job as a computer architecture designer. At your interview, you tell the panel that you have some real neat ideas for some cool processors. For example, you have an instruction that can set an individual bit in memory. The format of your instruction is This instruction sets a bit in
What effective address is generated by the instruction LDR rO, [r2, -r3, LSL #1]?
Some machines have a find-first-one instruction that counts the location of the first bit set to 1 within the word. Write an ARM sequence of instructions that takes the word in rO and puts the locations of the first bit set to 1 in rl. Count from the left, so that if bit 31 is set, the value
What is the meaning of sign-extension in the context of copying data from one location to another?
Why is sign-extension an important issue when we use a LDR instruction to load a register from memory but of no importance when we use an STR to store a register in memory?
Assume that r2 contains the initial value 0000100016. Explain the effect of each of the following six instructions, and give the value in r2 after each instruction executes. a. STR b. STR C. STR d. STR r1, [12] r1, [r2, #8] r1, [r2, #8] ! r1, [r2] #8 e. STR rl, [r2, r0, LSL #8] f. STMFD r2!, {rl,
Most RISC processors do not include a block move instruction. What are the advantages and disadvantages of the ARM's LDM and STM instructions?
Without using the ARM's multiplication instruction, write one or more instructions (using ADD, SUB, and shifting) to multiply by the following integers. a. 33 b. 1025 C. 4095
A word consists of the bytes b4, b3, b2, and bl. Write a function to invert the bits of b3 and clear the bits of b2, leaving all other bits unchanged.
Write suitable ARM code to implement. if x y call PQR else call ZXY
Write an ARM assembly language program that scans a string terminated by the null byte OxOO and copies the string from a source location pointed at by rO to a destination pointed at by rl.
Write a program to copy text from the location pointed at by rO to the location pointed at by rl. The copied version must be in reverse order. Assume the string you are copying is non-null (it contains at least one character) and that it is terminated.
Write a program to reverse a character string with an odd number of characters pointed at by rO. Assume the string you are copying is non-null (it contains at least one character) and that it is terminated by OxOD (the number of characters included the terminator). You must not use an additional
What does the following code do? TEQ RSBMI ro, #0 ro, ro, #0
What is the meaning of the following mnemonics (and what do they do)? a. LDRSH b. RSBLES C. CMPS d. MRS r0, CPSR
What is the meaning of sign-extension in the context of copying data from one location to another?
What is wrong with the following instruction? MLA r0, r0, r1, r2
What, in the contest of assembly language, is a pseudo-operation?
Explain the meaning of the following two ARM pseudo-operations. What do they do and why have they been implemented? a. ADR r0, table b. LDR = r0, 0x1234FEDC
Suppose you execute LDR, r0=0xl2345678 on an ARM machine followed by STR r0, [rll where rl = 0xlO00. Now, suppose you do a byte read to the same address with LDRB r2, [rl]. What would the value be in r2 if.(a) The ARM was big-endian configured(b) It was little-endian configured?
Write an ARM assembly language program to determine whether a string of characters with an odd length is a palindrome (for example, mom) under the following constraints. a. The string of ASIC-encoded characters is stored in memory. b. At the start of the program, register rl contains the address
A singly linked list (Figure P3.53), whose first element is pointed at by r0, consists of elements whose head is a 32-bit address pointing to the next element in the list and a variable-length tail. The tail may be of any length greater than four bytes. The last element in the list points to the
Explain what this fragment of code does instruction by instruction and what purpose it achieves ( assuming that register r0 is the register of interest). Note that the data in r0 must not be 0 on entry. loop MOV MOVS ADDCC BCC rl, #0 ro, ro, LSL #1 rl, r1, #1 loop
The following is a loop expressed in ARM code. The code is wrong. Why? ; Loop counter - ten times round the loop Next ADD rl, rl, ro; add loop counter to total MOV r0, #10 SUB ro, r0, #1 BEQ Next ; decrement loop counter ; continue until all done
We need to swap the following registers. Do this using block moves. Before r1 r2 r3 r4 r5 r6 r7 After r3 r4 r5 r6 r7 r1 r2
Why is the assembly language structure (format) of ARM's block move instructions inconsistent with ARM's normal assembler conventions? If you were redesigning ARM's assembly language, how might you express these operations (remember, changing the assembly language does not change the
Register r15 is the program counter. You can use it with certain instructions such as a MOV (e.g., MOV pc, r14). However, r15 cannot be used in conjunction with most data processing instructions. Why?
What is a stack frame and why is it so important?
What is the difference between a stack pointer and a frame pointer?
We said that any computer program can be constructed using a single instruction that performs a subtraction and branches on negative. Discuss the accuracy of this statement.
SBN a,b,c is defined as: [a] = [a] - [b]; if [ a] :5 0, then branch to c. Using only a SBN destination, source, target, (subtract source from destination and branch to target on negative) instruction, implement the following primitives a. MOVE X, Y b. ADD X, Y ;copy the contents of memory
Eight-bit microprocessors and classic CISC computers like the Intel IA32 and 68K families have variable-length instructions. What are the advantages of computer architectures with instructions of different lengths? What are the disadvantages?
Investigate the variations in multiply and divide instructions supported by three different microprocessor families. Why is there more variation in the ways in which multiplication and division are performed than in, for example, addition?
Data movement requires that data be moved from a source to a destination. What are the practical issues that a designer must be aware of when implementing a data move instruction?
Some data movement instructions re-order the sequence of bits that comprise the data elements they are moving. Why?
Suppose you have a basic instruction set with typical primitive arithmetic and logical operations (add, sub, and, or, not, xor, Isl, and lsr). How would you move a 32-bit word from memory location a to location b and reorder the bytes from PQRS to SQRP using only this instruction set?
Two instructions provided by the 68K CISC processors are LEA (load effective address) and PEA (push an effective address on the stack). What do these instructions do, and how are they used in practice?
Why do some processors provide support for double-precision shifting operations? What other double-precision operations are supported by processors?
What is bounds testing, and how does the 68020 implement it? If you were a processor designer, would you implement bounds testing? Can you think of other ways of incorporating bounds testing in an architecture?
Investigate several microprocessors, and describe how they support the mechanization of control loops.
What instructions are missing from microprocessor instruction sets? This question asks you to think about the type of operations computers perform, and to think about what primitives could usefully be incorporated to accelerate the calculation.
What is memory indirect addressing, and how is it used?
Why do so few processors implement memory indirect addressing?
The 68020 supports both preindexed and postindexed memory indirect addressing modes. What, in this context, are preindexing and postindexing? If only one of these addressing modes could be implemented, which do you think is the better alternative? Explain your reasoning with examples.
What is compressed code, in the sense of Thumb?
Do compressed architectures represent an advance or a regression in computer development? Use examples to justify your answer.
The two compressed architectures described in this chapter reduce instruction size by restricting the range of literals, and by reducing the size of the instruction set and the number of registers.
We said that a problem with variable length instructions is that you cannot determine instruction boundaries further down the instruction stream, because you have to decode each instruction individually to determine its length. Modern high-performance computers look ahead in the code in order to
The 68K family has separate general-purpose address and data registers. What are the differences between these two types of registers? Since most other computers with general-purpose register sets do not distinguish in hardware between data and addresses, was Motorola's idea a good one or a bad
Suppose that a BFFFO operation is applied to the data structure in Figure P4.30. What value would be loaded into the destination register assuming that the base byte address is 800? FIGURE P4.30 Base address 800 801 1, O 802 7 Bit field 803 0 0 0 0 0 0 0 0 0 1 1 01 Cengage Leaming 2014
Suppose that multiple-precision shifts did not exist and that you could use only logical shifts. How would you implement a double-precision shift by using only single-precision shifts?
The 68020's CHK2 and CMP2 instructions are rather nice because they let you compare a register against two bounds in order to perform array subscript checking at run time. Unfortunately, they are expensive, because they require two words to be read from memory (the upper and lower bounds) and that
A 68020 assembly language instruction that uses a bit field operation with a complex effective address is: Write a suitable sequence of ARM processor operations that would perform the same action. Assume that the target address is a 32-bit word. BFFFO ([8, A0, D1*4], 4) (D2, D3 }, D4
If you have an m-bit register, loading an m-bit constant presents a bit of a problem. Discuss how ISA designers have gone about solving this problem in both CISC and RISC domains.
Why are RISC programs that perform similar functions to CISC programs generally larger?
How do the instruction encodings of ARM processors and MIPS processors differ?
What is multimedia?
A computer lacks a division instruction and performs iteratively using the technique described on page 300. Suppose we wish to evaluate 327/940. How many cycles of iteration would it take to get an accuracy of ten decimal places?
What is the difference between lossless and lossy compression?
Is the popular ZIP compression technique lossy or lossless?
What are the characteristics of data streams (i.e., the type of data) that are used in lossy compression techniques?

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