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computer science
computer architecture

Questions and Answers of Computer Architecture

Using the powers of each digit in base 8, convert the decimal number 6026 to octal.
Perform the following binary divisions:a. 110√1010001001b. 1011√11000000000
Multiply the following binary numbers together:a.1101× 101b.11011× 1011
Add the following binary numbers:a.101101101+ 10011011b.110111111+110111111c.11010011+ 10001010d. 1101 1010 111+ 101e. Repeat the previous additions by converting each
a. Create the hexadecimal multiplication table.b. Use the hexadecimal table in Figure 3.8 to perform the following addition: 2AB3+ 35DCc. Add the following numbers:1 FF9+ F7d.
Locate a current reference that lists the important protocols that are members of the TCP/IP protocol suite. Explain how each protocol contributes to the operation and use of the Internet.
Protocols and standards are an important feature of networks. Why is this so?
Although there is substantial overlap between protocols and standards there are protocols that are not standards and standards that are not protocols. With the help of a dictionary, identify the
The human body is an example of an object that can be represented as a system. Consider the various ways in which you could represent the human body as a system. Select a representation and identify
Consider this textbook. Using the detailed table of contents as a reference, we can represent this textbook as a hierarchical system. As a first pass, we can define this book by the five component
Thinking in terms of systems allows us to analyze situations that are too complicated for us to understand as a whole. What specific characteristics and features of system thinking make this possible?
Figure 2.8 illustrates the basic architecture for a three-tier database system. This system can be viewed as an IPO system. What is the input for this system? What environmental element generates the
It is common to represent network connections in IT systems as a cloud. (See, for example, Figures 2.6, 2.7, 2.8, and 2.9). The cloud is obviously an abstraction as we defined abstraction in this
Suppose that you have been hired to develop a website-based sales system for a large international retail sales firm. Discuss some environmental issues that are specific to the Web design of your
Consider a home theatre system consisting of a television set, a receiver, a DVD player, speakers, and any other components you wish to include. Draw a system diagram for this system. Include both
a. Determine the power of each digit for five-digit numbers in base 6.b. Use your results from part (a) to convert the base 6 number 245316 to decimal.
Determine the power of each digit for four-digit numbers in base 16. Which place digits in base 2 have the same power?
Convert the following hexadecimal numbers to decimal:a. 4Eb. 3D7c. 3D70
Some older computers used an 18-bit word to store numbers. What is the decimal range for this word size?
How many bits will it take to represent the decimal number 3,175,000? How many bytes will it take to store this number?
a. Create addition and multiplication tables for base 12 arithmetic. Use alphabetic characters to represent digits 10 and larger.b. Using your tables from part (a), perform the following
Construct a table like that shown in Figure C.25 to check for WAW stalls in the MIPS FP pipeline of Figure C.35. Do not consider FP divides.Figure C.25 Integer unit EX FP/integer multiply H0000 M2
Suppose MIPS had only one register set. Construct the forwarding table for the FP and integer instructions using the format of Figure C.26. Ignore FP and integer divides.Figure C.26 Pipeline register
Create a table showing the R4000 integer hazard detection using the same format as that shown in Figure C.25. Include only the MIPS instructions we considered in Figure C.26.Figure C.26 Pipeline
Create a table showing the forwarding logic for the R4000 integer pipeline using the same format as that shown in Figure C.26. Include only the MIPS instructions we considered in Figure C.26.Figure
In this problem, we will explore how deepening the pipeline affects performance in two ways: faster clock cycle and increased stalls due to data and control hazards. Assume that the original machine
We will now add support for register-memory ALU operations to the classic five-stage RISC pipeline. To offset this increase in complexity, all memory addressing will be restricted to register
A reduced hardware implementation of the classic five-stage RISC pipeline might use the EX stage hardware to perform a branch instruction comparison and then not actually deliver the branch target PC
We begin with a computer implemented in single-cycle implementation. When the stages are split by functionality, the stages do not require exactly the same amount of time. The original machine had a
For this problem, you will create a series of small snippets that illustrate the issues that arise when using functional units with different latencies. For each one, draw a timing diagram similar to
Some memory systems handle TLB misses in software (as an exception), while others use hardware for TLB misses.a. What are the trade-offs between these two methods for handling TLB misses?b. Will TLB
A program is running on a computer with a four-entry fully associative (micro) translation lookaside buffer (TLB):The following is a trace of virtual page numbers accessed by a program. For each
Excluding some instructions from entering the cache can reduce conflict misses.a. Sketch a program hierarchy where parts of the program would be better excluded from entering the instruction cache.
Consider a two-level memory hierarchy made of L1 and L2 data caches. Assume that both caches use write-back policy on write hit and both have the same block size. List the actions taken in response
Increasing a cache’s associativity (with all other parameters kept constant), statistically reduces the miss rate. However, there can be pathological cases where increasing a cache’s
The LRU replacement policy is based on the assumption that if address A1 is accessed less recently than address A2 in the past, then A2 will be accessed again before A1 in the future. Hence, A2 is
In systems with a write-through L1 cache backed by a writeback L2 cache instead of main memory, a merging write buffer can be simplified. Explain how this can be done. Are there situations where
Converting miss rate (misses per reference) into misses per instruction relies upon two factors: references per instruction fetched and the fraction of fetched instructions that actually commits.a.
The design of MIPS provides for 32 general-purpose registers and 32 floating-point registers. If registers are good, are more registers better? List and discuss as many trade-offs as you can that
Consider this high-level code sequence of three statements:A = B + C;B = A + C;D = A €“ B;Use the technique of copy propagation (see Figure A.20) to transform the code sequence to the point
Because of the massive scale of WSCs, it is very important to properly allocate network resources based on the workloads that are expected to be run. Different allocations can have significant
Datacenter Networking: Map- Reduce and WSC are a powerful combination to tackle large-scale data processing; for example, Google in 2008 sorted one petabyte (1 PB) of records in a little more than 6
Consider a social networking Web site with 100 million active users posting updates about themselves (in text and pictures) as well as browsing and interacting with updates in their social networks.
Multiprocessors and clusters usually show performance increases as you increase the number of the processors, with the ideal being nx speedup for n processors. The goal of this biased benchmark is to
When trying to perform detailed performance evaluation of a multiprocessor system, system designers use one of three tools: analytical models, trace-driven simulation, and execution-driven
Prove that in a two-level cache hierarchy, where L1 is closer to the processor, inclusion is maintained with no extra action if L2 has at least as much associativity as L1, both caches use line
The memory consistency model provides a specification of how the memory system will appear to the programmer. Consider the following code segment, where the initial values area. At the end of the
One performance optimization commonly used is to pad synchronization variables to not have any other useful data in the same cache line as the synchronization variable. Construct a pathological
A directory controller can send invalidates for lines that have been replaced by the local cache controller. To avoid such messages and to keep the directory consistent, replacement hints are used.
Assume a directory-based cache coherence protocol. The directory currently has information that indicates that processor P1 has the data in “exclusive” mode. If the directory now gets a request
How would you change the code of an application to avoid false sharing? What might be done by a compiler and what might require programmer directives?
This exercise studies the impact of aggressive techniques to exploit instruction-level parallelism in the processor when used in the design of shared-memory multiprocessor systems. Consider two
One proposed solution for the problem of false sharing is to add a valid bit per word. This would allow the protocol to invalidate a word without removing the entire block, letting a processor keep a
Assume that we have a function for an application of the form F(i, p), which gives the fraction of time that exactly i processors are usable given that a total of p processors is available. That
Assume a hypothetical GPU with the following characteristics:■ Clock rate 1.5 GHz■ Contains 16 SIMD processors, each containing 16 single-precision floatingpoint units■ Has 100 GB/sec off-chip
List and describe at least four factors that influence the performance of GPU kernels. In other words, which runtime behaviors that are caused by the kernel code cause a reduction in resource
Assume a GPU architecture that contains 10 SIMD processors. Each SIMD instruction has a width of 32 and each SIMD processor contains 8 lanes for single-precision arithmetic and load/store
How well do you expect this code to perform on a GPU? Explain your answer. 22 21 18 19 20 12 13 14 15 16 17 10 11 2 3 4 5
Now assume that we can use scatter-gather loads and stores (LVI and SVI). Assume that tiPL, tiPR, clL, clR, and clP are arranged consecutively in memory. For example, if seq_length==500, the tiPR
Assume that the vector reduction instruction is executed on the vector functional unit, similar to a vector add instruction. Show how the code sequence lays out in convoys assuming a single instance
Assuming seq_length == 500, what is the dynamic instruction count for both implementations?
correlating branch predictor uses the behavior of the most recent m executed branches to choose from 2m predictors, each of which is an nbit predictor. A two-level local predictor works in a similar
Popek and Goldberg’s definition of a virtual machine said that it would be indistinguishable from a real machine except for its performance. In this question, we will use that definition to find
Whenever a computer is idle, we can either put it in stand by (where DRAM is still active) or we can let it hibernate. Assume that, to hibernate, we have to copy just the contents of DRAM to a
To access data from a typical DRAM, we first have to activate the appropriate row. Assume that this brings an entire page of size 8 KB to the row buffer. Then we select a particular column from the
When making changes to optimize part of a processor, it is often the case that speeding up one type of instruction comes at the cost of slowing down something else. For example, if we put in a
In this exercise, assume that we are considering enhancing a machine by adding vector hardware to it. When a computation is run in vector mode on the vector hardware, it is 10 times faster than the
Server farms such as Google and Yahoo! provide enough compute capacity for the highest request rate of the day. Imagine that most of the time these servers operate at only 60% capacity. Assume
Your company is trying to choose between purchasing the Opteron or Itanium 2. You have analyzed your company’s applications, and 60% of the time it will be running applications similar to wupwise,
Assume that we make an enhancement to a computer that improves some mode of execution by a factor of 10. Enhanced mode is used 50% of the time, measured as a percentage of the execution time when the
When parallelizing an application, the ideal speedup is speeding up by the number of processors. This is limited by two things: percentage of the application that can be parallelized and the cost of
You are designing a system for a real-time application in which specific deadlines must be met. Finishing the computation faster gains nothing. You find that your system can execute the necessary
One challenge for architects is that the design created today will require several years of implementation, verification, and testing before appearing on the market. This means that the architect
It costs $1 billion to build a new fabrication facility. You will be selling a range of chips from that factory, and you need to decide how much capacity to dedicate to each chip. Your Woods chip

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