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Computer Organization And Design MIPS Edition The Hardware/Software Interface 6th Edition David A. Patterson, John L. Hennessy - Solutions
Consider the following loop.LOOP: ld $s0, 0($s3)ld $s1, 8($s3)add $s2, $s0, $s1 addi $s3, $s3, -16 bnez $s2, LOOPAssume that perfect branch prediction is used (no stalls due to control hazards), that there are no delay slots, that the pipeline has full forwarding support, and that branches are
Which of the two pipeline diagrams below better describes the operation of the pipeline's hazard detection unit? Why? Choice 1:ld x11, 0(x12): IF ID EX ME WBadd x13, x11, x14: IF ID EX..ME WBor x15, x16, x17: IF ID..EX ME WBChoice 2:ld x11, 0(x12): IF ID EX ME WBadd x13, x11, x14: IF ID..EX ME
If we change load/store instructions to use a register (without an offset) as the address, these instructions no longer need to use the ALU.(See Exercise 4.15.) As a result, the MEM and EX stages can be overlapped and the pipeline has only four stages.1. How will the reduction in pipeline depth
Consider the fragment of MIPS assembly below:sd $s5, 12($s3)Id $s5, 8($s3)sub $s4, $s2, $s1beqz $s4, labeladd $s2, $s0, $s1sub $s2, $s6, $s1Suppose we modify the pipeline so that it has only one memory (that handles both instructions and data). In this case, there will be a structural hazard every
Consider a version of the pipeline from Section 4.6 that does not handle data hazards (i.e., the programmer is responsible for addressing data hazards by inserting NOP instructions where necessary). Suppose that (after optimization) a typical n-instruction program requires an additional 4*n NOP
Add NOP instructions to the code below so that it will run correctly on a pipeline that does not handle data hazards.addi $s0, $s1, 5add $s2, $s0, $s1addi $s3, $s0, 15add $s4, $s2, $s1
Assume that $s0 is initialized to 11 and $s1 is initialized to 22. Suppose you executed the code below on a version of the pipeline from Section 4.6 that does not handle data hazards (i.e., the programmer is responsible for addressing data hazards by inserting NOP instructions where necessary).
For which instructions (if any) is the Imm Gen block on the critical path?
Someone has asked about the possibility of data hazards occur ring through memory, as opposed to through a register. Which of the following statements about such hazards are true?1. Since memory accesses only occur in the MEM stage, all memory operations are done in the same order as instruction
Examine the difficulty of adding a proposed ss rt, rs, imm (Store Sum) instruction to MIPS.Interpretation: Mem[Reg[rt]=Reg[rs]+immediate1. Which new functional blocks (if any) do we need for this instruction?2. Which existing functional blocks (if any) require modification?3. What new data paths do
Someone has proposed moving the write for a result from an ALU instruction from the WB to the MEM stage, pointing out that this would reduce the maximum length of forwards from an ALU instruction by one cycle. Which of the following are accurate reasons not to consider such a change?
Examine the difficulty of adding a proposed swap rs, rt instruction to MIPS.Interpretation: Reg[rt] = Reg[rs]; Reg[rs] = Reg[rt]1. Which new functional blocks (if any) do we need for this instruction?2. Which existing functional blocks (if any) require modification?3. What new data paths do we need
Are the following statements true or false?1. The Intel Core i7 uses a multiple-issue pipeline to directly execute x86 instructions.2. Both the A53 and the Core i7 use dynamic multiple issue.3. The Core i7 microarchitecture has many more registers than x86 requires.4. The Intel Core i7 uses less
When processor designers consider a possible improvement to the processor datapath, the decision usually depends on the cost/performance trade-off. In the following three problems, assume that we are beginning with the datapath from Figure 4.21, the latencies from Exercise 4.7, and the following
State whether the following techniques or components are associated primarily with a software- or hardware-based approach to exploiting ILP. In some cases, the answer may be both.1. Branch prediction2. Multiple issue3. VLIW4. Superscalar5. Dynamic scheduling6. Out-of-order execution7. Speculation8.
Which exception should be recognized first in this sequence?1. add $1, $2, $1 # arithmetic overflow2. XXX $1, $2, $1 # undefined instruction3. sub $1, $2, $1 # hardware error
Consider the addition of a multiplier to the CPU shown in Figure 4.21. This addition will add 300 ps to the latency of the ALU, but will reduce the number of instructions by 5% (because there will no longer be a need to emulate the multiply instruction). 1. What is the clock cycle time with and
Suppose you could build a CPU where the clock cycle time was different for each instruction. What would the speedup of this new CPU be over the CPU presented in Figure 4.21 given the instruction mix below?Figure 4.21 PC Add Read address Instruction [31-0] Instruction [31-26] Instruction
Consider three branch prediction schemes: predict not taken, predict taken, and dynamic prediction. Assume that they all have zero penalty when they predict correctly and two cycles when they are wrong. Assume that the average predict accuracy of the dynamic predictor is 90%. Which predictor is the
Problems in this exercise assume that the logic blocks used to implement a processor’s datapath have the following latencies:“Register read” is the time needed after the rising clock edge for the new register value to appear on the output. This value applies to the PC only. “Register
A group of students were debating the efficiency of the five-stage pipeline when one student pointed out that not all instructions are active in every stage of the pipeline. After deciding to ignore the effects of hazards, they made the following four statements. Which ones are correct?1. Allowing
Does not discuss I-type instructions like addi or andi.1. What additional logic blocks, if any, are needed to add I-type instructions to the CPU shown in Figure 4.21? Add any necessary logic blocks to Figure 4.21 and explain their purpose.2. List the values of the signals generated by the control
Explain each of the “don’t cares” in Figure 4.18.Figure 4.18 Instruction R-format Tw SW beg RegDst 1 0 X X ALUSIC 0 1 1 0 Memto- Reg 0 1 X X Reg- Write 1 1 0 0 Mem- Mem- Read Write 0 1 0 0 0 0 1 OH 0 Branch 0 0 0 1 ALUOp1 1 000 ALUOPO 0 0 0 1
For each code sequence below, state whether it must stall, can avoid stalls using only forwarding, or can execute without stalling or forwarding. Sequence 1 Inst0,0(3t) add $t1, $t0, sto Sequence 2 add $t1, $t0, sto addi $t2, $t0, #5 addi St4, $t1, #5 Sequence 3 addi $t1, $t0, #1 addi $t2, $t0,
1. True or false: Since the jump instruction does not depend on the register values or on computing the branch target address, it can be completed during the second state, rather than waiting until the third.2. True, false, or maybe: The control signal PCWriteCond can be replaced by PCSource[0].
Look at the control signals in Figure 4.22. Can you combine any together? Can any control signal output in the figure be replaced by the inverse of another? If so, can you use one signal for the other without adding an inverter?Figure 4.22 Input or output Inputs Outputs Signal
When silicon chips are fabricated, defects in materials (e.g., silicon) and manufacturing errors can result in defective circuits. A very common defect is for one signal wire to get “broken” and always register a logical 0. This is often called a “stuck-at-0” fault.1. Which instructions
I. Which of the following is correct for a load instruction? Refer to Figure 4.10.a. MemtoReg should be set to cause the data from memory to be sent to the register file.b. MemtoReg should be set to cause the correct register destination to be sent to the register file.c. We do not care about the
Consider the following instruction mix:1. What fraction of all instructions use data memory?2. What fraction of all instructions use instruction memory?3. What fraction of all instructions use the sign extend?4. What is the sign extend doing during cycles in which its output is not needed?
True or false: Because the register file is both read and written on the same clock cycle, any MIPS datapath using edge-triggered writes must have more than one copy of the register file.
How many of the five classic components of a computer—shown in Figures 4.1 and 4.2 include?Figure 4.1 Figure 4.2 PC Add Address Instruction Instruction memory Add Data Register # Registers Register # Register # ALU Address Data Data memory
What is the minimum number of cycles needed to completely execute n instructions on a CPU with a k stage pipeline?Justify your formula.
Which of the advantages of an interpreter over a translator do you think was most important for the designers of Java?1. Ease of writing an interpreter2. Better error messages3. Smaller object code4. Machine independence
For the following C statement, write a minimal sequence of MIPS assembly instructions that does the identical operation. Assume $t0 = A and $s0 is the base address of C.A = C[0]
Suppose the program counter (PC) is set to 0x20000000.1. What range of addresses can be reached using the MIPS jump-and-link (jai) instruction? (In other words, what is the set of possible values for the PC after the jump instruction executes?)2. What range of addresses can be reached using the
Consider a proposed new instruction named rpt. This instruction combines a loop’s condition check and counter decrement into a single instruction. For example, rpt $s0, loop would do the following:if (x29 > 0) {x29 = x29 − 1;goto loop }1. If this instruction were to be implemented in the MIPS
Consider the following instruction:Instruction: and rd, rsl, rs2 Interpretation: Reg[rd] = Reg[rs1] AND Reg[rs2]1.What are the values of control signals generated by the control in Figure 4.10 for this instruction?2. Which resources (blocks) perform a useful function for this instruction?3. Which
The revised IEEE 754-2008 standard added a 16-bit floating-point format with five exponent bits. What do you think is the likely range of numbers it could represent? 1. 1.0000 00 × 2⁰ to 1.1111 1111 11 × 231,0 2. +1.0000 0000 0 × 2-¹4 to ± 1.1111 1111 1 × 2¹5, ± 0, ± ∞, NaN X ± 3.
Some programming languages allow two’s complement integer arithmetic on variables declared byte and half, whereas MIPS only has integer arithmetic operations on full words. As we recall from Chapter 2, MIPS does have data transfer operations for bytes and halfwords. What MIPS instructions should
Write the MIPS assembly code to implement the following C code as an atomic “set max” operation using the lI/sc instructions. Here, the argument shvar contains the address of a shared variable, which should be replaced by x if x is greater than the value it points to: void setmax(int* shvar,
For the following code:lbu $t0, 0($t1)sw $t0, 0($t2)Assume that the register $t1 contains the address 0x10000000 and the data at address is 0x11223344.1. What value is stored in 0x10000004 on a big-endian machine?2. What value is stored in 0x10000004 on a little-endian machine?
I. What is the range of addresses for conditional branches in MIPS (K = 1024)?1. Addresses between 0 and 64 K−12. Addresses between 0 and 256 K−13. Addresses up to about 32 K before the branch to about 32 K after4. Addresses up to about 128 K before the branch to about 128 K after II. What
I. Which of the following statements about characters and strings in C and Java are true?1. A string in C takes about half the memory as the same string in Java.2. Strings are just an informal name for single-dimension arrays of characters in C and Java.3. Strings in C and Java use null (0) to
Which of the following statements about C and Java are generally true?1. C programmers manage data explicitly, while it’s automatic in Java.2. C leads to more pointer bugs and memory leak bugs than does Java.
What MIPS instruction does this represent? Choose from one of the four options below. op rs 8 00 rt 9 rd 10 shamt funct 0 34 1. sub $t0, $t1,$t2 2. add $t2, $t0, $t1 3. sub $t2, $t1, $t0 4. sub $t2, $t0, $t1 If a person is age 40ten what is their age in hexidecimal?
What is the decimal value of this 64-bit two’s complement number? 1111 1111 11111111 1111 11111111 1111 11111111 1111 11111111 11111111 1000 2)-8 3) -16, 4) 18,446,744,073,709,551.608. What is the decimal value if it is instead a 64-bit unsigned number?
Given the importance of registers, what is the rate of increase in the number of registers in a chip over time?1. Very fast: They increased as fast as Moore’s law, which predicted doubling the number of transistors on a chip every 24 months.2. Very slow: Since programs are usually distributed in
Write a single C statement that corresponds to the two MIPS assembly instructions below.add f, g, h add f, i, f
For the following C statement, what is the corresponding MIPS assembly code? Assume that the C variables f, g, and h, have already been placed in registers $s0, $s1, and $s2, respectively. Use a minimal number of MIPS assembly instructions.f = g + (h – 5);
For a given function, which programming language likely takes the most lines of code? Put the three representations below in order.1. Java 2. C 3. MIPS assembly language
Consider the table given next, which tracks several performance indicators for Intel desktop processors since 2010.The “Tech” column shows the minimum feature size of each processor’s fabrication process. Assume that the die size has remained relatively constant and the number of transistors
Consider the following performance measurements for a program: Measurement Instruction count Clock rate CPI Computer A 10 billion 4 GHz 1.0 Computer B 8 billion 4 GHz 1.1 a. Which computer has the higher MIPS rating? b. Which computer is faster?
Suppose we know that an application that uses both personal mobile devices and the Cloud is limited by network performance. For the following changes, state whether only the throughput improves, both response time and throughput improve, or neither improves.
A key factor in determining the cost of an integrated circuit is volume. Which of the following are reasons why a chip made in high volume should cost less?1. With high volumes, the manufacturing process can be tuned to a particular design, increasing the yield.2. It is less work to design a
The seven great ideas in computer architecture are similar to ideas from other fields. Match the seven ideas from computer architecture, “Use Abstraction to Simplify Design”, “Make the Common Case Fast”, “Performance via Parallelism”, “Performance via Pipelining”, “Performance via
I. C has many statements for decisions and loops, while MIPS has few. Which of the following do or do not explain this imbalance? Why?1. More decision statements make code easier to read and understand.2. Fewer decision statements simplify the task of the underlying layer that is responsible for
Which operations can isolate a field in a word?1. AND 2. A shift left followed by a shift right
A given application written in Java runs 15 seconds on a desktop processor. A new Java compiler is released that requires only 0.6 as many instructions as the old compiler. Unfortunately, it increases the CPI by 1.1. How fast can we expect the application to run using this new compiler? Pick the
Semiconductor DRAM memory, flash memory, and disk storage differ significantly. For each technology, list its volatility, approximate relative access time, and approximate relative cost compared to DRAM.
List and describe three types of computers.
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![PC Add Read address Instruction (31-01 Instruction [31-26] Instruction [25-21] Instruction [20-16]](https://dsd5zvtm8ll6.cloudfront.net/images/question_images/1703/7/6/8/476658d719c50eb01703768474996.jpg)
![PC Add Read address Instruction [31-0] Instruction [31-26] Instruction [25-21] Instruction [20-16]](https://dsd5zvtm8ll6.cloudfront.net/images/question_images/1703/7/6/7/655658d6e67c2ecb1703767654663.jpg)
