You are building an instruction cache for a MIPS processor. It has a total capacity of 4C
Question:
You are building an instruction cache for a MIPS processor. It has a total capacity of 4C = 2c+2 bytes. It is N = 2n -way set associative (N ≥ 8), with a block size of b = 2b′ bytes (b ≥ 8). Give your answers to the following questions in terms of these parameters.
(a) Which bits of the address are used to select a word within a block?
(b) Which bits of the address are used to select the set within the cache?
(c) How many bits are in each tag?
(d) How many tag bits are in the entire cache?
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a b c Each tag is 32 c2n bits ...View the full answer
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Related Book For 
Digital Design and Computer Architecture
ISBN: 978-0123944245
2nd edition
Authors: David Harris, Sarah Harris
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