A D flip-flop has a setup time of 5 ns, a hold time of 3 ns, and

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A D flip-flop has a setup time of 5 ns, a hold time of 3 ns, and a propagation delay from the rising edge of the clock to the change in flip-flop output in the range of 6 to 12 ns. An OR gate delay is in the range of 1 to 4 ns.

(a) What is the minimum clock period for proper operation of the following circuit?

х CLK

(b) What is the earliest time after the rising clock edge at which X is allowed to change?

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Digital Systems Design Using Verilog

ISBN: 978-1285051079

1st edition

Authors: Charles Roth, Lizy K. John, Byeong Kil Lee

Question Posted: Jan 08, 2019 12:43 PM

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A D flip-flop has a setup time of 5 ns, a hold time of 3 ns, and

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х CLK

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Digital Systems Design Using Verilog

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