Write Verilog code to test a Mealy sequential circuit with one input (X) and one output (Z). The code should include the Mealy circuit as a component. Assume the Mealy circuit changes state on the rising edge of CLK. Your test code should generate a clock with a 100-ns period. The code should apply the following test sequence:

X = 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 0

X should change 10 ns after the rising edge of CLK. Your test code should read Z at an appropriate time and should verify that the following output sequence was generated:

Z = 1, 0, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0

Report an error if the output sequence from the Mealy circuit is incorrect; otherwise, report “sequence correct.” Complete the following architecture for the tester:
module tester;
reg CLK;reg[11:0]X;
reg[11:0]Z;
initial
begin
X = 12'b011011011100;
Z = 12'b100110110110;
CLK = 1;
end
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endmodule