Write a Verilog test bench that will test the Verilog code for the sequential circuit of Figure 2-58. Your test bench should generate all 10 possible input sequences (0000, 0001, 0010, . . .,1001) and should verify that the output sequences are correct. Remember that the components have a 10-ns delay. The input should be changed 1/4 of a clock period after the rising edge of the clock, and the output should be read at the appropriate time. Report “Pass” if all sequences are correct; otherwise, report “Fail.”