1. Cache Accesses (6 points - Correctness): Complete the following table for each of the below cache configurations: (a) 256 byte, 2-way set associative cache with 32-byte block size. (b) 256 byte, fully associative cache with 32-byte block size. For each access fill the last two columns with the type of cache miss if it is a miss (Just write hit if it's a cache hit). Use Least Recently Used (LRU) as the replacement policy. Show tag, index and offset bits calculation in the box below to get full credits. Cache (a) (Type of Cache Miss) Cache (b) (Type of Cache Miss) Address (in binary) 1010 0000 1010 0000 1100 0001 1100 0100 1101 0001 0010 0110 0010 1100 1110 1010 0110 0001 0010 1110 1111 1001 0000 0000 1010 0000 1010 0001 1101 1010 0100 0011 1100 0001 1100 1100 1100 1011 0110 1100 1111 1000 1100 0000 1101 1010 0100 1011 1100 1100 1000 1110 1001 1001 0111 0010 0010 1100 1111 1010 1001 1001 0111 0011 1111 1001 0000 0001 1010 0000 1011 0001 0110 0001 0011 0010 1100 1100 1001 1000 1111 1000 1100 1110 1101 1010 0101 1011 1001 1111 0001 1111 0010 1100 1111 0010