5. A carry-select adder includes two 4-bit ripple carry adders per section. One ripple carry adder computes the sum and carry bits assuming the carry-in is 0 while the other computes them assuming the carry-in is 1. Once the carry-in is known, it is used as the select to multiplexors to choose the appropriate sum and carry-out bits (a) Draw a block diagram for one 4-bit section of a carry-select adder. Then, draw a block diagram of a 16-bit carry-select adder composed for four 4-bit sections (b) Assuming the delay of a 4-bit ripple carry adder is 4 and a multiplexor is 1, compare the delay of a 16-bit ripple carry adder to a 16-bit carry-select adder. (c) Describe a 4-bit section of a carry-select adder in Verilog. You should construct your design hierar- chically. Namely, you should write Verilog code for a full-adder and a multiplexor using primitive gates, instantiate your full-adder to build a 4-bit ripple carry adder, and, finally, instantiate your 4-bit ripple carry adder with multiplexors to construct your carry-select adder. Note: you will be using this Verilog code in Lab 2. Therefore, you should create your code electronically. It is also recommend that you simulate your carry-select adder. Doing so will ensure your code has no syntax errors and operates correctly. It will also give you a substantial head start on Lab 2