$5-$ Consider the sequential circuit whose state diagram is given below; design this circuit using J$-$K flip flop according to the following procedure.

a$)$ Write the state table.

b$)$ Derive the excitation and output equations.

c$)$ Draw the logic circuit.

d$)$ Draw the timing diagram for $5$ clocks when $\backslash (\backslash$mathrm$\{$X$\}=0\backslash )$ and the initial state is $(11).$