Below is a copy of the MIPS single cycle data path design and a table with the latencies of the execution units and blocks included in the datapath.

A) what is time for the critical datapath of MIPS ADD instruction?

B)What is the critical datapath for MIPS BEQ instruction?

Branch Add Add ALAJ Oberation Data Register # Registers Register # Address Instruction Instruction momory Banerne ALU- Address Zero Data memory XC 3 Register # Bes Data wiarniaeth Costrat en verwanwynwy wwwwwwwwwwwwane Branch Add Add ALAJ Oberation Data Register # Registers Register # Address Instruction Instruction momory Banerne ALU- Address Zero Data memory XC 3 Register # Bes Data wiarniaeth Costrat en verwanwynwy wwwwwwwwwwwwane