Question: Cache Memory Design [15 points] A MIPS processor has a 32-bit address bus and a cache memory of 4K(212) words. The cache is 2-way set

Cache Memory Design [15 points]
A MIPS processor has a 32-bit address bus and a cache memory of 4K(212) words.
The cache is 2-way set associative with a block size of 1 memory word. Here, each
word is 32-bit long.
(a) What bits of the address are used to select the set within the cache?
(b) How many bits are in each tag, and
(c) What is the actual size of the cache.
(d) Repeat part (c) if cache uses direct mapping (1-way set associative) with a block
size of 4 words.

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