Design Problem $3$

Write a VHDL module for a $4-$bit adder, with a carry$-$in and carry$-$out, using an overloaded addition operator and std$\_$logic$\_$vector inputs and outputs.

Design an $8-$bit subtracter with a borrow$-$out, using two of the $4-$bit adders you designed in $($a$),$ along with any necessary gates or inverters. Write a VHDL module for the subtracter.

Simulate your code and test it using the following inputs: $11011011-01110110,01110110-11011011$

Save your assignment using a naming convention that includes your first and last name and the activity number $($or description$).$ Do not add punctuation or special characters.