Hi i am trying to run this testbench file:

module testbench; // Inputs reg [4:0] A, B, C, D, E; // Outputs wire sum_of_difference; // Instantiate the DUT sum_of_difference dut ( .A(A), .B(B), .C(C), .D(D), .E(E), .sum_of_difference(sum_of_difference) ); // Test case 1 initial begin // Assign input values A = 5'b01010; B = 5'b01010; C = 5'b01010; D = 5'b01010; E = 5'b01010; // Wait for 1 ns #1; // Check output assert(sum_of_difference == 5'b10101); else $error("Test case 1 failed"); end

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and i am getting this error:

Error: (vlog-13069) C:/intelFPGA/17.0/sad2_tb.v(27): near "else": syntax error, unexpected else.

If someone could help me i would be gratefull!