in quartus prime

Design B: Implement a 4-bit ripple carry adder using structural VHDL. Please review the ripple carry adder for the design. You will need two VHDL files 'fulladd vhd' and 'adder4b.vhd' to implement the design. The 'fulladd vhd' file will implement a single-bit full adder. The 'adder4b.vhd' file will create four instances of the single-bit fulladd design with two 4-bit data inputs X and Y. The circuit is to have a 4-bit data output 'S'. Your design should also generate an output carry Cout'. You need to create test vectors in functional simulations to test your design for Designs A and B, in the prelab. Please refer to Appendix: Test Vectors