Let's assume that AMAT for a processor with first level cache $($L$1)$ is $2\mathrm{.}4$ clock cycles. If the data is in the L$1$ cache, it can be accessed for one clock cycle. If they are not found, $80$ cycles are needed for access. To improve AMAT by $65\%,$ an L$2$ cache will be added. This will be accessed for $6$ clock cycles. To achieve the required speedup, how often should the data be found in L$2?$