Question: library IEEE; use IEEE.STD _ LOGIC _ 1 1 6 4 . ALL; use IEEE.STD _ LOGIC _ ARITH.ALL; use IEEE.STD _ LOGIC _ UNSIGNED.ALL;
library IEEE;
use IEEE.STDLOGICALL;
use IEEE.STDLOGICARITH.ALL;
use IEEE.STDLOGICUNSIGNED.ALL;
entity ALU is
port
A B : in stdlogicvector downto ;
Opcode : in stdlogicvector downto ;
cin : in stdlogic;
Y : out stdlogicvector downto
;
end ALU;
architecture Behavioral of ALU is
begin
processA B Opcode, cin
begin
case Opcode is
when Y A;
when Y A ;
when Y A ;
when Y B;
when Y B ;
when Y B ;
when Y A B;
when Y A B cin;
when Y not A;
when Y not B;
when Y A and B;
when Y A or B;
when Y A nand B;
when Y A nor B;
when Y A xor B;
when Y A xnor B;
when others Y others ;
end case;
end process;
end Behavioral;
structural vhdl description
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