Problem $\backslash$# $1$

Assume the following RISC$-$V assembly code:

$```$

addi x$12,$ x$12,0$

TOP: slli x$5,$ x$12,3$

add x$6,$ x$10,$ x$5$

ld x$7,0($x$6)$

ld x$29,8($x$6)$

sub x$30,$ x$7,$ x$29$

add x$31,$ x$11,$ x$5$

sd x$30,0($x$31)$

addi x$12,$ x$12,2$

bne x$12,$ x$13,$ TOP

$```$

Assume the two$-$issue, statically scheduled processor that has the following properties:

$-$ One instruction must be a memory operation; the other must be an arithmetic$/$logic instruction or a branch.

$-$ The processor has all possible forwarding paths between stages $($including paths to the ID stage for branch resolution$).$

$-$ The processor has perfect branch prediction.

$-$ Two instructions may not issue together in a packet if one depends on the other.

$-$ If a stall is necessary, both instructions in the issue packet must stall.

$1.$ Draw an instruction scheduling diagram on how RISC$-$V code given above executes on the two$-$issue processor. Assume that the loop exits after one iteration.

$2.$ What is the speedup of going from a one$-$issue to a two$-$issue processor? $($compare IPC for the two cases$).$