$\backslash (\backslash$square $\backslash )$ Consider the figure below, the block of $2$ps means the clock skew :

$-$ Assume:

$>$ Setup time $\backslash$& Hold time are $5$ps

$\backslash (>\backslash )$ Clock uncertainty $\backslash (=1\backslash )$ ps

$\backslash (>\backslash$mathrm$\{$Tcq$\}=1\backslash$mathrm$\{$ps$\}\backslash )$

$\backslash (>\backslash )$ Clock period $\backslash (=20\backslash )$ ps

$-($a$)$ Determine whether a timing violation exists in the circuit. Calculate both the data arrival time$($start from clk source$)$ and data required time$($start from clk source$),$ and specify the type of timing violation if present.

$-($b$)$ How to fix all the timing violations by adding clock buffers and delay cells? Please explain clearly how to fix these violations and recalculate the new data arrival time and data required time. Also, provide a figure to demonstrate how to add clock buffers and delay cells in the circuit.

$3$