Suppose the logic blocks in a processor have the following latencies... a) In a single cycle, non-pipelined processor, what is the minimum time between instructions for an application executing only R-type instructions? b) In a single cycle, non-pipelined processor, what is the minimum time between instructions for an application executing R, I, and J-type instructions? c) If the logic blocks above are each implemented as individual pipeline stages, what would be the minimum time between instructions for this pipelined CPU if hazards are ignored